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author | liamwhite <liamwhite@users.noreply.github.com> | 2023-03-23 15:00:19 +0100 |
---|---|---|
committer | GitHub <noreply@github.com> | 2023-03-23 15:00:19 +0100 |
commit | c41a4baf06efe935f08331bc6f8ff6d80dc088f5 (patch) | |
tree | a6580d41bd440b240b2f60db38fdeec60fca2eff /src/core/arm | |
parent | Merge pull request #9962 from Kelebek1/disable_srgb (diff) | |
parent | kernel: use KTypedAddress for addresses (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/core/arm/arm_interface.cpp | 10 | ||||
-rw-r--r-- | src/core/arm/arm_interface.h | 8 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.cpp | 6 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.h | 6 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 8 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.h | 6 |
6 files changed, 22 insertions, 22 deletions
diff --git a/src/core/arm/arm_interface.cpp b/src/core/arm/arm_interface.cpp index 4a331d4c1..be3f55cd2 100644 --- a/src/core/arm/arm_interface.cpp +++ b/src/core/arm/arm_interface.cpp @@ -168,21 +168,21 @@ void ARM_Interface::LoadWatchpointArray(const WatchpointArray& wp) { } const Kernel::DebugWatchpoint* ARM_Interface::MatchingWatchpoint( - VAddr addr, u64 size, Kernel::DebugWatchpointType access_type) const { + u64 addr, u64 size, Kernel::DebugWatchpointType access_type) const { if (!watchpoints) { return nullptr; } - const VAddr start_address{addr}; - const VAddr end_address{addr + size}; + const u64 start_address{addr}; + const u64 end_address{addr + size}; for (size_t i = 0; i < Core::Hardware::NUM_WATCHPOINTS; i++) { const auto& watch{(*watchpoints)[i]}; - if (end_address <= watch.start_address) { + if (end_address <= GetInteger(watch.start_address)) { continue; } - if (start_address >= watch.end_address) { + if (start_address >= GetInteger(watch.end_address)) { continue; } if ((access_type & watch.type) == Kernel::DebugWatchpointType::None) { diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h index c40771c97..8e40702cc 100644 --- a/src/core/arm/arm_interface.h +++ b/src/core/arm/arm_interface.h @@ -78,7 +78,7 @@ public: * @param addr Start address of the cache range to clear * @param size Size of the cache range to clear, starting at addr */ - virtual void InvalidateCacheRange(VAddr addr, std::size_t size) = 0; + virtual void InvalidateCacheRange(u64 addr, std::size_t size) = 0; /** * Notifies CPU emulation that the current page table has changed. @@ -149,9 +149,9 @@ public: */ virtual void SetPSTATE(u32 pstate) = 0; - virtual VAddr GetTlsAddress() const = 0; + virtual u64 GetTlsAddress() const = 0; - virtual void SetTlsAddress(VAddr address) = 0; + virtual void SetTlsAddress(u64 address) = 0; /** * Gets the value within the TPIDR_EL0 (read/write software thread ID) register. @@ -214,7 +214,7 @@ protected: static void SymbolicateBacktrace(Core::System& system, std::vector<BacktraceEntry>& out); const Kernel::DebugWatchpoint* MatchingWatchpoint( - VAddr addr, u64 size, Kernel::DebugWatchpointType access_type) const; + u64 addr, u64 size, Kernel::DebugWatchpointType access_type) const; virtual Dynarmic::HaltReason RunJit() = 0; virtual Dynarmic::HaltReason StepJit() = 0; diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp index 2a7570073..aa92d3fc3 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp @@ -155,7 +155,7 @@ public: return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0); } - bool CheckMemoryAccess(VAddr addr, u64 size, Kernel::DebugWatchpointType type) { + bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) { if (!check_memory_access) { return true; } @@ -397,7 +397,7 @@ u64 ARM_Dynarmic_32::GetTlsAddress() const { return cp15->uro; } -void ARM_Dynarmic_32::SetTlsAddress(VAddr address) { +void ARM_Dynarmic_32::SetTlsAddress(u64 address) { cp15->uro = static_cast<u32>(address); } @@ -439,7 +439,7 @@ void ARM_Dynarmic_32::ClearInstructionCache() { jit.load()->ClearCache(); } -void ARM_Dynarmic_32::InvalidateCacheRange(VAddr addr, std::size_t size) { +void ARM_Dynarmic_32::InvalidateCacheRange(u64 addr, std::size_t size) { jit.load()->InvalidateCacheRange(static_cast<u32>(addr), size); } diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h index d24ba2289..bce695daf 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.h +++ b/src/core/arm/dynarmic/arm_dynarmic_32.h @@ -41,8 +41,8 @@ public: void SetVectorReg(int index, u128 value) override; u32 GetPSTATE() const override; void SetPSTATE(u32 pstate) override; - VAddr GetTlsAddress() const override; - void SetTlsAddress(VAddr address) override; + u64 GetTlsAddress() const override; + void SetTlsAddress(u64 address) override; void SetTPIDR_EL0(u64 value) override; u64 GetTPIDR_EL0() const override; @@ -60,7 +60,7 @@ public: void ClearExclusiveState() override; void ClearInstructionCache() override; - void InvalidateCacheRange(VAddr addr, std::size_t size) override; + void InvalidateCacheRange(u64 addr, std::size_t size) override; void PageTableChanged(Common::PageTable& new_page_table, std::size_t new_address_space_size_in_bits) override; diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index 7229fdc2a..67073c84d 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp @@ -117,7 +117,7 @@ public: } void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op, - VAddr value) override { + u64 value) override { switch (op) { case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: { static constexpr u64 ICACHE_LINE_SIZE = 64; @@ -199,7 +199,7 @@ public: return parent.system.CoreTiming().GetClockTicks(); } - bool CheckMemoryAccess(VAddr addr, u64 size, Kernel::DebugWatchpointType type) { + bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) { if (!check_memory_access) { return true; } @@ -452,7 +452,7 @@ u64 ARM_Dynarmic_64::GetTlsAddress() const { return cb->tpidrro_el0; } -void ARM_Dynarmic_64::SetTlsAddress(VAddr address) { +void ARM_Dynarmic_64::SetTlsAddress(u64 address) { cb->tpidrro_el0 = address; } @@ -500,7 +500,7 @@ void ARM_Dynarmic_64::ClearInstructionCache() { jit.load()->ClearCache(); } -void ARM_Dynarmic_64::InvalidateCacheRange(VAddr addr, std::size_t size) { +void ARM_Dynarmic_64::InvalidateCacheRange(u64 addr, std::size_t size) { jit.load()->InvalidateCacheRange(addr, size); } diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h index ed1a5eb96..e83599e82 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.h +++ b/src/core/arm/dynarmic/arm_dynarmic_64.h @@ -38,8 +38,8 @@ public: void SetVectorReg(int index, u128 value) override; u32 GetPSTATE() const override; void SetPSTATE(u32 pstate) override; - VAddr GetTlsAddress() const override; - void SetTlsAddress(VAddr address) override; + u64 GetTlsAddress() const override; + void SetTlsAddress(u64 address) override; void SetTPIDR_EL0(u64 value) override; u64 GetTPIDR_EL0() const override; @@ -53,7 +53,7 @@ public: void ClearExclusiveState() override; void ClearInstructionCache() override; - void InvalidateCacheRange(VAddr addr, std::size_t size) override; + void InvalidateCacheRange(u64 addr, std::size_t size) override; void PageTableChanged(Common::PageTable& new_page_table, std::size_t new_address_space_size_in_bits) override; |