From 699b67d7cfacb48c65df3a6f7e5adc55aebd4c2a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 14 May 2015 15:14:02 -0400 Subject: dyncom: Handle some MSR variants individually This is necessary, as hint instructions will be recognized as MSR, which is pretty bad. --- src/core/arm/dyncom/arm_dyncom_dec.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/core/arm/dyncom/arm_dyncom_dec.cpp') diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 411850f0f..d0d37bea0 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -181,7 +181,11 @@ const ISEITEM arm_instruction[] = { { "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 }, { "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 }, { "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 }, - { "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 }, + { "msr", 3, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000001 }, + { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 19, 0x00000004 }, + { "msr", 5, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 19, 19, 0x00000001, 16, 17, 0x00000000 }, + { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 17, 0x00000001 }, + { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 17, 17, 0x00000001 }, { "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 }, { "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 }, { "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 }, @@ -375,6 +379,10 @@ const ISEITEM arm_exclusion_code[] = { { "mrc", 0, 6, 0 }, { "mcr", 0, 0, 0 }, { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, { "ldrb", 0, 0, 0 }, { "strb", 0, 0, 0 }, { "ldr", 0, 0, 0 }, -- cgit v1.2.3