From a8c41c50d3f7a1c2871487862f68925db8b5e27f Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Fri, 26 Feb 2021 21:41:46 -0500
Subject: shader: Implement POPC

---
 src/shader_recompiler/backend/spirv/emit_spirv.h           | 2 ++
 src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 8 ++++++++
 2 files changed, 10 insertions(+)

(limited to 'src/shader_recompiler/backend')

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 90afbcc90..64c8e9ef6 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -228,6 +228,8 @@ Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count)
 Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
 Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
 Id EmitBitReverse32(EmitContext& ctx, Id value);
+Id EmitBitCount32(EmitContext& ctx, Id value);
+Id EmitBitwiseNot32(EmitContext& ctx, Id a);
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 406df1b78..e49ca7bde 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -106,6 +106,14 @@ Id EmitBitReverse32(EmitContext& ctx, Id value) {
     return ctx.OpBitReverse(ctx.U32[1], value);
 }
 
+Id EmitBitCount32(EmitContext& ctx, Id value) {
+    return ctx.OpBitCount(ctx.U32[1], value);
+}
+
+Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
+    return ctx.OpNot(ctx.U32[1], a);
+}
+
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
     return ctx.OpSLessThan(ctx.U1, lhs, rhs);
 }
-- 
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