From 6c51f496320f698e123207c09ca61e55180a31b5 Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Sun, 28 Mar 2021 22:23:45 -0400
Subject: shader: Implement FSWZADD

---
 .../translate/impl/floating_point_swizzled_add.cpp | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp

(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp')

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
new file mode 100644
index 000000000..e42921a21
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
@@ -0,0 +1,44 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/common_types.h"
+#include "shader_recompiler/exception.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+void TranslatorVisitor::FSWZADD(u64 insn) {
+    union {
+        u64 raw;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<28, 8, u64> swizzle;
+        BitField<38, 1, u64> ndv;
+        BitField<39, 2, FpRounding> round;
+        BitField<44, 1, u64> ftz;
+        BitField<47, 1, u64> cc;
+    } const fswzadd{insn};
+
+    if (fswzadd.ndv != 0) {
+        throw NotImplementedException("FSWZADD NDV");
+    }
+
+    const IR::F32 src_a{GetFloatReg8(insn)};
+    const IR::F32 src_b{GetFloatReg20(insn)};
+    const IR::U32 swizzle{ir.Imm32(static_cast<u32>(fswzadd.swizzle))};
+
+    const IR::FpControl fp_control{
+        .no_contraction{false},
+        .rounding{CastFpRounding(fswzadd.round)},
+        .fmz_mode{fswzadd.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
+    };
+
+    const IR::F32 result{ir.FSwizzleAdd(src_a, src_b, swizzle, fp_control)};
+    F(fswzadd.dest_reg, result);
+
+    if (fswzadd.cc != 0) {
+        throw NotImplementedException("FSWZADD CC");
+    }
+}
+
+} // namespace Shader::Maxwell
-- 
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