From 112b8f00f0da0e031bb62a7a7a44469d3a5518a6 Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Sun, 21 Mar 2021 01:32:02 -0400
Subject: shader: Add FP64 register load/store helpers

---
 .../frontend/maxwell/translate/impl/impl.cpp       | 27 ++++++++++++++++------
 1 file changed, 20 insertions(+), 7 deletions(-)

(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index c9af83010..2d2f6f9c6 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -25,6 +25,13 @@ IR::F32 TranslatorVisitor::F(IR::Reg reg) {
     return ir.BitCast<IR::F32>(X(reg));
 }
 
+IR::F64 TranslatorVisitor::D(IR::Reg reg) {
+    if (!IR::IsAligned(reg, 2)) {
+        throw NotImplementedException("Unaligned source register {}", reg);
+    }
+    return IR::F64{ir.PackDouble2x32(ir.CompositeConstruct(X(reg), X(reg + 1)))};
+}
+
 void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) {
     ir.SetReg(dest_reg, value);
 }
@@ -33,6 +40,16 @@ void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) {
     X(dest_reg, ir.BitCast<IR::U32>(value));
 }
 
+void TranslatorVisitor::D(IR::Reg dest_reg, const IR::F64& value) {
+    if (!IR::IsAligned(dest_reg, 2)) {
+        throw NotImplementedException("Unaligned destination register {}", dest_reg);
+    }
+    const IR::Value result{ir.UnpackDouble2x32(value)};
+    for (int i = 0; i < 2; i++) {
+        X(dest_reg + i, IR::U32{ir.CompositeExtract(result, i)});
+    }
+}
+
 IR::U32 TranslatorVisitor::GetReg8(u64 insn) {
     union {
         u64 raw;
@@ -68,13 +85,9 @@ IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) {
 IR::F64 TranslatorVisitor::GetDoubleReg20(u64 insn) {
     union {
         u64 raw;
-        BitField<20, 8, IR::Reg> src;
-    } const index{insn};
-    const IR::Reg reg{index.src};
-    if (!IR::IsAligned(reg, 2)) {
-        throw NotImplementedException("Unaligned source register {}", reg);
-    }
-    return ir.PackDouble2x32(ir.CompositeConstruct(X(reg), X(reg + 1)));
+        BitField<20, 8, IR::Reg> index;
+    } const reg{insn};
+    return D(reg.index);
 }
 
 static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) {
-- 
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