From 08d751d88278542dcbd03e5f9cbf76588475e49d Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 15 Oct 2018 01:58:30 -0300 Subject: gl_shader_decompiler: Setup base for half float unpacking and setting --- src/video_core/engines/shader_bytecode.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/video_core/engines/shader_bytecode.h') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 9a59b65b3..d6d46d277 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -335,6 +335,26 @@ enum class IsberdMode : u64 { enum class IsberdShift : u64 { None = 0, U16 = 1, B32 = 2 }; +enum class HalfType : u64 { + H0_H1 = 0, + F32 = 1, + H0_H0 = 2, + H1_H1 = 3, +}; + +enum class HalfMerge : u64 { + H0_H1 = 0, + F32 = 1, + Mrg_H0 = 2, + Mrg_H1 = 3, +}; + +enum class HalfPrecision : u64 { + None = 0, + FTZ = 1, + FMZ = 2, +}; + enum class IpaInterpMode : u64 { Linear = 0, Perspective = 1, -- cgit v1.2.3 From d46e2a6e7ac22661d6debe090c8c6b25d565613a Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 15 Oct 2018 02:04:31 -0300 Subject: gl_shader_decompiler: Implement non-immediate HADD2 and HMUL2 instructions --- src/video_core/engines/shader_bytecode.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src/video_core/engines/shader_bytecode.h') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index d6d46d277..f84b9883c 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -573,6 +573,22 @@ union Instruction { BitField<49, 1, u64> negate_a; } alu_integer; + union { + BitField<39, 1, u64> ftz; + BitField<32, 1, u64> saturate; + BitField<49, 2, HalfMerge> merge; + + BitField<43, 1, u64> negate_a; + BitField<44, 1, u64> abs_a; + BitField<47, 2, HalfType> type_a; + + BitField<31, 1, u64> negate_b; + BitField<30, 1, u64> abs_b; + BitField<47, 2, HalfType> type_b; + + BitField<35, 2, HalfType> type_c; + } alu_half; + union { BitField<40, 1, u64> invert; } popc; @@ -1165,6 +1181,10 @@ public: LEA_RZ, LEA_IMM, LEA_HI, + HADD2_C, + HADD2_R, + HMUL2_C, + HMUL2_R, POPC_C, POPC_R, POPC_IMM, @@ -1238,6 +1258,7 @@ public: ArithmeticImmediate, ArithmeticInteger, ArithmeticIntegerImmediate, + ArithmeticHalf, Bfe, Shift, Ffma, @@ -1409,6 +1430,10 @@ private: INST("001101101101----", Id::LEA_IMM, Type::ArithmeticInteger, "LEA_IMM"), INST("010010111101----", Id::LEA_RZ, Type::ArithmeticInteger, "LEA_RZ"), INST("00011000--------", Id::LEA_HI, Type::ArithmeticInteger, "LEA_HI"), + INST("0111101-1-------", Id::HADD2_C, Type::ArithmeticHalf, "HADD2_C"), + INST("0101110100010---", Id::HADD2_R, Type::ArithmeticHalf, "HADD2_R"), + INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"), + INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), -- cgit v1.2.3 From d93cdc27505f86633d3a947fb48a6bcb92d790d0 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 15 Oct 2018 02:07:16 -0300 Subject: gl_shader_decompiler: Implement HADD2_IMM and HMUL2_IMM --- src/video_core/engines/shader_bytecode.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'src/video_core/engines/shader_bytecode.h') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index f84b9883c..3fbdd20b8 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -589,6 +589,31 @@ union Instruction { BitField<35, 2, HalfType> type_c; } alu_half; + union { + BitField<39, 2, HalfPrecision> precision; + BitField<39, 1, u64> ftz; + BitField<52, 1, u64> saturate; + BitField<49, 2, HalfMerge> merge; + + BitField<43, 1, u64> negate_a; + BitField<44, 1, u64> abs_a; + BitField<47, 2, HalfType> type_a; + } alu_half_imm; + + union { + BitField<29, 1, u64> first_negate; + BitField<20, 9, u64> first; + + BitField<56, 1, u64> second_negate; + BitField<30, 9, u64> second; + + u32 PackImmediates() const { + // Immediates are half floats shifted. + constexpr u32 imm_shift = 6; + return static_cast((first << imm_shift) | (second << (16 + imm_shift))); + } + } half_imm; + union { BitField<40, 1, u64> invert; } popc; @@ -1183,8 +1208,10 @@ public: LEA_HI, HADD2_C, HADD2_R, + HADD2_IMM, HMUL2_C, HMUL2_R, + HMUL2_IMM, POPC_C, POPC_R, POPC_IMM, @@ -1259,6 +1286,7 @@ public: ArithmeticInteger, ArithmeticIntegerImmediate, ArithmeticHalf, + ArithmeticHalfImmediate, Bfe, Shift, Ffma, @@ -1432,8 +1460,10 @@ private: INST("00011000--------", Id::LEA_HI, Type::ArithmeticInteger, "LEA_HI"), INST("0111101-1-------", Id::HADD2_C, Type::ArithmeticHalf, "HADD2_C"), INST("0101110100010---", Id::HADD2_R, Type::ArithmeticHalf, "HADD2_R"), + INST("0111101-0-------", Id::HADD2_IMM, Type::ArithmeticHalfImmediate, "HADD2_IMM"), INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"), INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"), + INST("0111100-0-------", Id::HMUL2_IMM, Type::ArithmeticHalfImmediate, "HMUL2_IMM"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), -- cgit v1.2.3 From 3d65aa4caf88a440eeaf2082b1f5ca3e2c41317c Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 15 Oct 2018 02:08:31 -0300 Subject: gl_shader_decompiler: Implement HFMA2 instructions --- src/video_core/engines/shader_bytecode.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'src/video_core/engines/shader_bytecode.h') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 3fbdd20b8..23bfd8988 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -614,6 +614,29 @@ union Instruction { } } half_imm; + union { + union { + BitField<37, 2, HalfPrecision> precision; + BitField<32, 1, u64> saturate; + + BitField<30, 1, u64> negate_c; + BitField<35, 2, HalfType> type_c; + } rr; + + BitField<57, 2, HalfPrecision> precision; + BitField<52, 1, u64> saturate; + + BitField<49, 2, HalfMerge> merge; + + BitField<47, 2, HalfType> type_a; + + BitField<56, 1, u64> negate_b; + BitField<28, 2, HalfType> type_b; + + BitField<51, 1, u64> negate_c; + BitField<53, 2, HalfType> type_reg39; + } hfma2; + union { BitField<40, 1, u64> invert; } popc; @@ -1212,6 +1235,10 @@ public: HMUL2_C, HMUL2_R, HMUL2_IMM, + HFMA2_CR, + HFMA2_RC, + HFMA2_RR, + HFMA2_IMM_R, POPC_C, POPC_R, POPC_IMM, @@ -1290,6 +1317,7 @@ public: Bfe, Shift, Ffma, + Hfma2, Flow, Synch, Memory, @@ -1464,6 +1492,10 @@ private: INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"), INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"), INST("0111100-0-------", Id::HMUL2_IMM, Type::ArithmeticHalfImmediate, "HMUL2_IMM"), + INST("01110---1-------", Id::HFMA2_CR, Type::Hfma2, "HFMA2_CR"), + INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"), + INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"), + INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), -- cgit v1.2.3 From 4fc8ad67bfc99d1c80c95c0df54360a55a6be011 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 15 Oct 2018 02:09:40 -0300 Subject: gl_shader_decompiler: Implement HSETP2_R --- src/video_core/engines/shader_bytecode.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/video_core/engines/shader_bytecode.h') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 23bfd8988..a6e764ea4 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -800,6 +800,23 @@ union Instruction { BitField<45, 4, PredOperation> op; // op with pred39 } csetp; + union { + BitField<35, 4, PredCondition> cond; + BitField<49, 1, u64> h_and; + BitField<6, 1, u64> ftz; + BitField<45, 2, PredOperation> op; + BitField<3, 3, u64> pred3; + BitField<0, 3, u64> pred0; + BitField<43, 1, u64> negate_a; + BitField<44, 1, u64> abs_a; + BitField<47, 2, HalfType> type_a; + BitField<31, 1, u64> negate_b; + BitField<30, 1, u64> abs_b; + BitField<28, 2, HalfType> type_b; + BitField<42, 1, u64> neg_pred; + BitField<39, 3, u64> pred39; + } hsetp2; + union { BitField<39, 3, u64> pred39; BitField<42, 1, u64> neg_pred; @@ -1239,6 +1256,7 @@ public: HFMA2_RC, HFMA2_RR, HFMA2_IMM_R, + HSETP2_R, POPC_C, POPC_R, POPC_IMM, @@ -1325,6 +1343,7 @@ public: FloatSetPredicate, IntegerSet, IntegerSetPredicate, + HalfSetPredicate, PredicateSetPredicate, PredicateSetRegister, Conversion, @@ -1496,6 +1515,7 @@ private: INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"), INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"), INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"), + INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP_R"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), -- cgit v1.2.3 From 6312eec5ef650ca5363ef4cfa08c2d38ffb6a0fe Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Mon, 15 Oct 2018 02:10:15 -0300 Subject: gl_shader_decompiler: Implement HSET2_R --- src/video_core/engines/shader_bytecode.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/video_core/engines/shader_bytecode.h') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index a6e764ea4..39ae065de 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -831,6 +831,21 @@ union Instruction { BitField<56, 1, u64> neg_imm; } fset; + union { + BitField<49, 1, u64> bf; + BitField<35, 3, PredCondition> cond; + BitField<50, 1, u64> ftz; + BitField<45, 2, PredOperation> op; + BitField<43, 1, u64> negate_a; + BitField<44, 1, u64> abs_a; + BitField<47, 2, HalfType> type_a; + BitField<31, 1, u64> negate_b; + BitField<30, 1, u64> abs_b; + BitField<28, 2, HalfType> type_b; + BitField<42, 1, u64> neg_pred; + BitField<39, 3, u64> pred39; + } hset2; + union { BitField<39, 3, u64> pred39; BitField<42, 1, u64> neg_pred; @@ -1257,6 +1272,7 @@ public: HFMA2_RR, HFMA2_IMM_R, HSETP2_R, + HSET2_R, POPC_C, POPC_R, POPC_IMM, @@ -1343,6 +1359,7 @@ public: FloatSetPredicate, IntegerSet, IntegerSetPredicate, + HalfSet, HalfSetPredicate, PredicateSetPredicate, PredicateSetRegister, @@ -1516,6 +1533,7 @@ private: INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"), INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"), INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP_R"), + INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), -- cgit v1.2.3