From f7c7f422c6995a31c1a16c0865bbe13bb38469a3 Mon Sep 17 00:00:00 2001
From: Yuri Kunde Schlesner <yuriks@yuriks.net>
Date: Sat, 28 Jan 2017 13:03:13 -0800
Subject: VideoCore: Split shader regs from Regs struct

---
 src/video_core/pica.h | 97 ++-------------------------------------------------
 1 file changed, 3 insertions(+), 94 deletions(-)

(limited to 'src/video_core/pica.h')

diff --git a/src/video_core/pica.h b/src/video_core/pica.h
index 765fa5dd4..099dc84f0 100644
--- a/src/video_core/pica.h
+++ b/src/video_core/pica.h
@@ -22,6 +22,7 @@
 #include "video_core/regs_lighting.h"
 #include "video_core/regs_pipeline.h"
 #include "video_core/regs_rasterizer.h"
+#include "video_core/regs_shader.h"
 #include "video_core/regs_texturing.h"
 
 namespace Pica {
@@ -57,97 +58,8 @@ struct Regs {
     FramebufferRegs framebuffer;
     LightingRegs lighting;
     PipelineRegs pipeline;
-
-    struct ShaderConfig {
-        BitField<0, 16, u32> bool_uniforms;
-
-        union {
-            BitField<0, 8, u32> x;
-            BitField<8, 8, u32> y;
-            BitField<16, 8, u32> z;
-            BitField<24, 8, u32> w;
-        } int_uniforms[4];
-
-        INSERT_PADDING_WORDS(0x4);
-
-        union {
-            // Number of input attributes to shader unit - 1
-            BitField<0, 4, u32> max_input_attribute_index;
-        };
-
-        // Offset to shader program entry point (in words)
-        BitField<0, 16, u32> main_offset;
-
-        /// Maps input attributes to registers. 4-bits per attribute, specifying a register index
-        u32 input_attribute_to_register_map_low;
-        u32 input_attribute_to_register_map_high;
-
-        unsigned int GetRegisterForAttribute(unsigned int attribute_index) const {
-            u64 map = ((u64)input_attribute_to_register_map_high << 32) |
-                      (u64)input_attribute_to_register_map_low;
-            return (map >> (attribute_index * 4)) & 0b1111;
-        }
-
-        BitField<0, 16, u32> output_mask;
-
-        // 0x28E, CODETRANSFER_END
-        INSERT_PADDING_WORDS(0x2);
-
-        struct {
-            enum Format : u32 {
-                FLOAT24 = 0,
-                FLOAT32 = 1,
-            };
-
-            bool IsFloat32() const {
-                return format == FLOAT32;
-            }
-
-            union {
-                // Index of the next uniform to write to
-                // TODO: ctrulib uses 8 bits for this, however that seems to yield lots of invalid
-                // indices
-                // TODO: Maybe the uppermost index is for the geometry shader? Investigate!
-                BitField<0, 7, u32> index;
-
-                BitField<31, 1, Format> format;
-            };
-
-            // Writing to these registers sets the current uniform.
-            u32 set_value[8];
-
-        } uniform_setup;
-
-        INSERT_PADDING_WORDS(0x2);
-
-        struct {
-            // Offset of the next instruction to write code to.
-            // Incremented with each instruction write.
-            u32 offset;
-
-            // Writing to these registers sets the "current" word in the shader program.
-            u32 set_word[8];
-        } program;
-
-        INSERT_PADDING_WORDS(0x1);
-
-        // This register group is used to load an internal table of swizzling patterns,
-        // which are indexed by each shader instruction to specify vector component swizzling.
-        struct {
-            // Offset of the next swizzle pattern to write code to.
-            // Incremented with each instruction write.
-            u32 offset;
-
-            // Writing to these registers sets the current swizzle pattern in the table.
-            u32 set_word[8];
-        } swizzle_patterns;
-
-        INSERT_PADDING_WORDS(0x2);
-    };
-
-    ShaderConfig gs;
-    ShaderConfig vs;
-
+    ShaderRegs gs;
+    ShaderRegs vs;
     INSERT_PADDING_WORDS(0x20);
 
     // Map register indices to names readable by humans
@@ -247,9 +159,6 @@ ASSERT_REG_POSITION(vs, 0x2b0);
 #undef ASSERT_REG_POSITION
 #endif // !defined(_MSC_VER)
 
-static_assert(sizeof(Regs::ShaderConfig) == 0x30 * sizeof(u32),
-              "ShaderConfig structure has incorrect size");
-
 // The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value
 // anyway.
 static_assert(sizeof(Regs) <= 0x300 * sizeof(u32),
-- 
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