diff options
23 files changed, 356 insertions, 237 deletions
diff --git a/src/citra/config.cpp b/src/citra/config.cpp index e9f3dfd5b..43175d6cb 100644 --- a/src/citra/config.cpp +++ b/src/citra/config.cpp @@ -66,6 +66,11 @@ void Config::ReadValues() { Settings::values.gpu_refresh_rate = glfw_config->GetInteger("Core", "gpu_refresh_rate", 30); Settings::values.frame_skip = glfw_config->GetInteger("Core", "frame_skip", 0); + // Renderer + Settings::values.bg_red = (float)glfw_config->GetReal("Renderer", "bg_red", 1.0); + Settings::values.bg_green = (float)glfw_config->GetReal("Renderer", "bg_green", 1.0); + Settings::values.bg_blue = (float)glfw_config->GetReal("Renderer", "bg_blue", 1.0); + // Data Storage Settings::values.use_virtual_sd = glfw_config->GetBoolean("Data Storage", "use_virtual_sd", true); diff --git a/src/citra/default_ini.h b/src/citra/default_ini.h index fc02a3ceb..1dd971926 100644 --- a/src/citra/default_ini.h +++ b/src/citra/default_ini.h @@ -41,6 +41,13 @@ gpu_refresh_rate = # 0 (default): No frameskip, 1: x2 frameskip, 2: x4 frameskip, 3: x8 frameskip, etc. frame_skip = +[Renderer] +# The clear color for the renderer. What shows up on the sides of the bottom screen. +# Must be in range of 0.0-1.0. Defaults to 1.0 for all. +bg_red = +bg_blue = +bg_green = + [Data Storage] # Whether to create a virtual SD card. # 1 (default): Yes, 0: No diff --git a/src/citra_qt/config.cpp b/src/citra_qt/config.cpp index ac250e0a5..fb85121b3 100644 --- a/src/citra_qt/config.cpp +++ b/src/citra_qt/config.cpp @@ -53,6 +53,12 @@ void Config::ReadValues() { Settings::values.frame_skip = qt_config->value("frame_skip", 0).toInt(); qt_config->endGroup(); + qt_config->beginGroup("Renderer"); + Settings::values.bg_red = qt_config->value("bg_red", 1.0).toFloat(); + Settings::values.bg_green = qt_config->value("bg_green", 1.0).toFloat(); + Settings::values.bg_blue = qt_config->value("bg_blue", 1.0).toFloat(); + qt_config->endGroup(); + qt_config->beginGroup("Data Storage"); Settings::values.use_virtual_sd = qt_config->value("use_virtual_sd", true).toBool(); qt_config->endGroup(); @@ -98,6 +104,13 @@ void Config::SaveValues() { qt_config->setValue("frame_skip", Settings::values.frame_skip); qt_config->endGroup(); + qt_config->beginGroup("Renderer"); + // Cast to double because Qt's written float values are not human-readable + qt_config->setValue("bg_red", (double)Settings::values.bg_red); + qt_config->setValue("bg_green", (double)Settings::values.bg_green); + qt_config->setValue("bg_blue", (double)Settings::values.bg_blue); + qt_config->endGroup(); + qt_config->beginGroup("Data Storage"); qt_config->setValue("use_virtual_sd", Settings::values.use_virtual_sd); qt_config->endGroup(); diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h index fe1e584ad..310663774 100644 --- a/src/core/arm/arm_interface.h +++ b/src/core/arm/arm_interface.h @@ -6,6 +6,7 @@ #include "common/common.h" #include "common/common_types.h" +#include "core/arm/skyeye_common/arm_regformat.h" namespace Core { struct ThreadContext; @@ -74,6 +75,20 @@ public: virtual void SetCPSR(u32 cpsr) = 0; /** + * Gets the value stored in a CP15 register. + * @param reg The CP15 register to retrieve the value from. + * @return the value stored in the given CP15 register. + */ + virtual u32 GetCP15Register(CP15Register reg) = 0; + + /** + * Stores the given value into the indicated CP15 register. + * @param reg The CP15 register to store the value into. + * @param value The value to store into the CP15 register. + */ + virtual void SetCP15Register(CP15Register reg, u32 value) = 0; + + /** * Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time) * @param ticks Number of ticks to advance the CPU core */ diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index cb1a410a0..1b1d01420 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp @@ -68,6 +68,14 @@ void ARM_DynCom::SetCPSR(u32 cpsr) { state->Cpsr = cpsr; } +u32 ARM_DynCom::GetCP15Register(CP15Register reg) { + return state->CP15[reg]; +} + +void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) { + state->CP15[reg] = value; +} + void ARM_DynCom::AddTicks(u64 ticks) { down_count -= ticks; if (down_count < 0) diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h index a7f95d307..822b3bbb9 100644 --- a/src/core/arm/dyncom/arm_dyncom.h +++ b/src/core/arm/dyncom/arm_dyncom.h @@ -22,6 +22,8 @@ public: void SetReg(int index, u32 value) override; u32 GetCPSR() const override; void SetCPSR(u32 cpsr) override; + u32 GetCP15Register(CP15Register reg) override; + void SetCP15Register(CP15Register reg, u32 value) override; void AddTicks(u64 ticks) override; diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index b0efd7194..65fe8a055 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -339,7 +339,7 @@ static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int ins unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); - unsigned int index; + unsigned int index = 0; unsigned int addr; unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); @@ -390,7 +390,7 @@ static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int in unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); - unsigned int index; + unsigned int index = 0; unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); @@ -605,7 +605,7 @@ static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, u unsigned int shift_imm = BITS(inst, 7, 11); unsigned int Rn = BITS(inst, 16, 19); unsigned int Rm = BITS(inst, 0, 3); - unsigned int index; + unsigned int index = 0; unsigned int addr; unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); @@ -1126,7 +1126,7 @@ int CondPassed(ARMul_State* cpu, unsigned int cond) { #define CFLAG cpu->CFlag #define VFLAG cpu->VFlag - int temp; + int temp = 0; switch (cond) { case 0x0: @@ -3700,7 +3700,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) { #define OPCODE_1 inst_cream->opcode_1 #define OPCODE_2 inst_cream->opcode_2 #define CRm inst_cream->crm - #define CP15_REG(n) cpu->CP15[CP15(n)] #define RD cpu->Reg[inst_cream->Rd] #define RD2 cpu->Reg[inst_cream->Rd + 1] #define RN cpu->Reg[inst_cream->Rn] diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 4ac827e0a..1d732fe84 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -16,6 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <cstring> +#include "core/mem_map.h" #include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armemu.h" @@ -66,6 +67,64 @@ void ARMul_SelectProcessor(ARMul_State* state, unsigned properties) ARMul_CoProInit(state); } +// Resets certain MPCore CP15 values to their ARM-defined reset values. +static void ResetMPCoreCP15Registers(ARMul_State* cpu) +{ + // c0 + cpu->CP15[CP15_MAIN_ID] = 0x410FB024; + cpu->CP15[CP15_TLB_TYPE] = 0x00000800; + cpu->CP15[CP15_PROCESSOR_FEATURE_0] = 0x00000111; + cpu->CP15[CP15_PROCESSOR_FEATURE_1] = 0x00000001; + cpu->CP15[CP15_DEBUG_FEATURE_0] = 0x00000002; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0] = 0x01100103; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1] = 0x10020302; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2] = 0x01222000; + cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3] = 0x00000000; + cpu->CP15[CP15_ISA_FEATURE_0] = 0x00100011; + cpu->CP15[CP15_ISA_FEATURE_1] = 0x12002111; + cpu->CP15[CP15_ISA_FEATURE_2] = 0x11221011; + cpu->CP15[CP15_ISA_FEATURE_3] = 0x01102131; + cpu->CP15[CP15_ISA_FEATURE_4] = 0x00000141; + + // c1 + cpu->CP15[CP15_CONTROL] = 0x00054078; + cpu->CP15[CP15_AUXILIARY_CONTROL] = 0x0000000F; + cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = 0x00000000; + + // c2 + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = 0x00000000; + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = 0x00000000; + cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = 0x00000000; + + // c3 + cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = 0x00000000; + + // c7 + cpu->CP15[CP15_PHYS_ADDRESS] = 0x00000000; + + // c9 + cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = 0xFFFFFFF0; + + // c10 + cpu->CP15[CP15_TLB_LOCKDOWN] = 0x00000000; + cpu->CP15[CP15_PRIMARY_REGION_REMAP] = 0x00098AA4; + cpu->CP15[CP15_NORMAL_REGION_REMAP] = 0x44E048E0; + + // c13 + cpu->CP15[CP15_PID] = 0x00000000; + cpu->CP15[CP15_CONTEXT_ID] = 0x00000000; + cpu->CP15[CP15_THREAD_UPRW] = 0x00000000; + cpu->CP15[CP15_THREAD_URO] = 0x00000000; + cpu->CP15[CP15_THREAD_PRW] = 0x00000000; + + // c15 + cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = 0x00000000; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = 0x00000000; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = 0x00000000; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = 0x00000000; + cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000; +} + /***************************************************************************\ * Call this routine to set up the initial machine state (or perform a RESET * \***************************************************************************/ @@ -80,6 +139,8 @@ void ARMul_Reset(ARMul_State* state) state->Bank = SVCBANK; FLUSHPIPE; + ResetMPCoreCP15Registers(state); + state->EndCondition = 0; state->ErrorCode = 0; diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index 6a11a5804..a68d53695 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp @@ -225,13 +225,10 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod if (crn == 13 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 2) - return cpu->CP15[CP15(CP15_THREAD_UPRW)]; + return cpu->CP15[CP15_THREAD_UPRW]; - // TODO: Whenever TLS is implemented, this should return - // "cpu->CP15[CP15(CP15_THREAD_URO)];" - // which contains the address of the 0x200-byte TLS if (opcode_2 == 3) - return Memory::KERNEL_MEMORY_VADDR; + return cpu->CP15[CP15_THREAD_URO]; } if (InAPrivilegedMode(cpu)) @@ -241,135 +238,135 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod if (crm == 0) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_MAIN_ID)]; + return cpu->CP15[CP15_MAIN_ID]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_CACHE_TYPE)]; + return cpu->CP15[CP15_CACHE_TYPE]; if (opcode_2 == 3) - return cpu->CP15[CP15(CP15_TLB_TYPE)]; + return cpu->CP15[CP15_TLB_TYPE]; if (opcode_2 == 5) - return cpu->CP15[CP15(CP15_CPU_ID)]; + return cpu->CP15[CP15_CPU_ID]; } else if (crm == 1) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)]; + return cpu->CP15[CP15_PROCESSOR_FEATURE_0]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)]; + return cpu->CP15[CP15_PROCESSOR_FEATURE_1]; if (opcode_2 == 2) - return cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)]; + return cpu->CP15[CP15_DEBUG_FEATURE_0]; if (opcode_2 == 4) - return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)]; + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0]; if (opcode_2 == 5) - return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)]; + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1]; if (opcode_2 == 6) - return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)]; + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2]; if (opcode_2 == 7) - return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)]; + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3]; } else if (crm == 2) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_ISA_FEATURE_0)]; + return cpu->CP15[CP15_ISA_FEATURE_0]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_ISA_FEATURE_1)]; + return cpu->CP15[CP15_ISA_FEATURE_1]; if (opcode_2 == 2) - return cpu->CP15[CP15(CP15_ISA_FEATURE_2)]; + return cpu->CP15[CP15_ISA_FEATURE_2]; if (opcode_2 == 3) - return cpu->CP15[CP15(CP15_ISA_FEATURE_3)]; + return cpu->CP15[CP15_ISA_FEATURE_3]; if (opcode_2 == 4) - return cpu->CP15[CP15(CP15_ISA_FEATURE_4)]; + return cpu->CP15[CP15_ISA_FEATURE_4]; } } if (crn == 1 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_CONTROL)]; + return cpu->CP15[CP15_CONTROL]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)]; + return cpu->CP15[CP15_AUXILIARY_CONTROL]; if (opcode_2 == 2) - return cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)]; + return cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL]; } if (crn == 2 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)]; + return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)]; + return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1]; if (opcode_2 == 2) - return cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)]; + return cpu->CP15[CP15_TRANSLATION_BASE_CONTROL]; } if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) - return cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)]; + return cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL]; if (crn == 5 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_FAULT_STATUS)]; + return cpu->CP15[CP15_FAULT_STATUS]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)]; + return cpu->CP15[CP15_INSTR_FAULT_STATUS]; } if (crn == 6 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_FAULT_ADDRESS)]; + return cpu->CP15[CP15_FAULT_ADDRESS]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_WFAR)]; + return cpu->CP15[CP15_WFAR]; } if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0) - return cpu->CP15[CP15(CP15_PHYS_ADDRESS)]; + return cpu->CP15[CP15_PHYS_ADDRESS]; if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) - return cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)]; + return cpu->CP15[CP15_DATA_CACHE_LOCKDOWN]; if (crn == 10 && opcode_1 == 0) { if (crm == 0 && opcode_2 == 0) - return cpu->CP15[CP15(CP15_TLB_LOCKDOWN)]; + return cpu->CP15[CP15_TLB_LOCKDOWN]; if (crm == 2) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)]; + return cpu->CP15[CP15_PRIMARY_REGION_REMAP]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)]; + return cpu->CP15[CP15_NORMAL_REGION_REMAP]; } } if (crn == 13 && crm == 0) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_PID)]; + return cpu->CP15[CP15_PID]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_CONTEXT_ID)]; + return cpu->CP15[CP15_CONTEXT_ID]; if (opcode_2 == 4) - return cpu->CP15[CP15(CP15_THREAD_PRW)]; + return cpu->CP15[CP15_THREAD_PRW]; } if (crn == 15) @@ -377,32 +374,32 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod if (opcode_1 == 0 && crm == 12) { if (opcode_2 == 0) - return cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)]; + return cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL]; if (opcode_2 == 1) - return cpu->CP15[CP15(CP15_CYCLE_COUNTER)]; + return cpu->CP15[CP15_CYCLE_COUNTER]; if (opcode_2 == 2) - return cpu->CP15[CP15(CP15_COUNT_0)]; + return cpu->CP15[CP15_COUNT_0]; if (opcode_2 == 3) - return cpu->CP15[CP15(CP15_COUNT_1)]; + return cpu->CP15[CP15_COUNT_1]; } if (opcode_1 == 5 && opcode_2 == 2) { if (crm == 5) - return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)]; + return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS]; if (crm == 6) - return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)]; + return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS]; if (crm == 7) - return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)]; + return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE]; } if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) - return cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)]; + return cpu->CP15[CP15_TLB_DEBUG_CONTROL]; } } @@ -420,38 +417,38 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c if (crn == 1 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_CONTROL)] = value; + cpu->CP15[CP15_CONTROL] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = value; + cpu->CP15[CP15_AUXILIARY_CONTROL] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = value; + cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value; } else if (crn == 2 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = value; + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = value; + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = value; + cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = value; } else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) { - cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = value; + cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = value; } else if (crn == 5 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_FAULT_STATUS)] = value; + cpu->CP15[CP15_FAULT_STATUS] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = value; + cpu->CP15[CP15_INSTR_FAULT_STATUS] = value; } else if (crn == 6 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = value; + cpu->CP15[CP15_FAULT_ADDRESS] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_WFAR)] = value; + cpu->CP15[CP15_WFAR] = value; } else if (crn == 7 && opcode_1 == 0) { @@ -459,56 +456,56 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c if (crm == 0 && opcode_2 == 4) { - cpu->CP15[CP15(CP15_WAIT_FOR_INTERRUPT)] = value; + cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value; } else if (crm == 4 && opcode_2 == 0) { // NOTE: Not entirely accurate. This should do permission checks. - cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = Memory::VirtualToPhysicalAddress(value); + cpu->CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value); } else if (crm == 5) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE)] = value; + cpu->CP15[CP15_INVALIDATE_INSTR_CACHE] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_MVA)] = value; + cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_INDEX)] = value; + cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value; else if (opcode_2 == 6) - cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE)] = value; + cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value; else if (opcode_2 == 7) - cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY)] = value; + cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value; } else if (crm == 6) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE)] = value; + cpu->CP15[CP15_INVALIDATE_DATA_CACHE] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value; + cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value; + cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value; } else if (crm == 7 && opcode_2 == 0) { - cpu->CP15[CP15(CP15_INVALIDATE_DATA_AND_INSTR_CACHE)] = value; + cpu->CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value; } else if (crm == 10) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE)] = value; + cpu->CP15[CP15_CLEAN_DATA_CACHE] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_MVA)] = value; + cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX)] = value; + cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value; } else if (crm == 14) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE)] = value; + cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value; + cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value; + cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value; } } else if (crn == 8 && opcode_1 == 0) @@ -518,104 +515,104 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c if (crm == 5) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_INVALIDATE_ITLB)] = value; + cpu->CP15[CP15_INVALIDATE_ITLB] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_INVALIDATE_ITLB_SINGLE_ENTRY)] = value; + cpu->CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH)] = value; + cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value; else if (opcode_2 == 3) - cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_MVA)] = value; + cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value; } else if (crm == 6) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_INVALIDATE_DTLB)] = value; + cpu->CP15[CP15_INVALIDATE_DTLB] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_INVALIDATE_DTLB_SINGLE_ENTRY)] = value; + cpu->CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH)] = value; + cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value; else if (opcode_2 == 3) - cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_MVA)] = value; + cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value; } else if (crm == 7) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_INVALIDATE_UTLB)] = value; + cpu->CP15[CP15_INVALIDATE_UTLB] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_INVALIDATE_UTLB_SINGLE_ENTRY)] = value; + cpu->CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH)] = value; + cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value; else if (opcode_2 == 3) - cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_MVA)] = value; + cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value; } } else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) { - cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = value; + cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = value; } else if (crn == 10 && opcode_1 == 0) { if (crm == 0 && opcode_2 == 0) { - cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = value; + cpu->CP15[CP15_TLB_LOCKDOWN] = value; } else if (crm == 2) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = value; + cpu->CP15[CP15_PRIMARY_REGION_REMAP] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = value; + cpu->CP15[CP15_NORMAL_REGION_REMAP] = value; } } else if (crn == 13 && opcode_1 == 0 && crm == 0) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_PID)] = value; + cpu->CP15[CP15_PID] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_CONTEXT_ID)] = value; + cpu->CP15[CP15_CONTEXT_ID] = value; else if (opcode_2 == 3) - cpu->CP15[CP15(CP15_THREAD_URO)] = value; + cpu->CP15[CP15_THREAD_URO] = value; else if (opcode_2 == 4) - cpu->CP15[CP15(CP15_THREAD_PRW)] = value; + cpu->CP15[CP15_THREAD_PRW] = value; } else if (crn == 15) { if (opcode_1 == 0 && crm == 12) { if (opcode_2 == 0) - cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = value; + cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value; else if (opcode_2 == 1) - cpu->CP15[CP15(CP15_CYCLE_COUNTER)] = value; + cpu->CP15[CP15_CYCLE_COUNTER] = value; else if (opcode_2 == 2) - cpu->CP15[CP15(CP15_COUNT_0)] = value; + cpu->CP15[CP15_COUNT_0] = value; else if (opcode_2 == 3) - cpu->CP15[CP15(CP15_COUNT_1)] = value; + cpu->CP15[CP15_COUNT_1] = value; } else if (opcode_1 == 5) { if (crm == 4) { if (opcode_2 == 2) - cpu->CP15[CP15(CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY)] = value; + cpu->CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value; else if (opcode_2 == 4) - cpu->CP15[CP15(CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY)] = value; + cpu->CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value; } else if (crm == 5 && opcode_2 == 2) { - cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = value; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value; } else if (crm == 6 && opcode_2 == 2) { - cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = value; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value; } else if (crm == 7 && opcode_2 == 2) { - cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = value; + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value; } } else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) { - cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = value; + cpu->CP15[CP15_TLB_DEBUG_CONTROL] = value; } } } @@ -623,18 +620,18 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c // Unprivileged registers if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4) { - cpu->CP15[CP15(CP15_FLUSH_PREFETCH_BUFFER)] = value; + cpu->CP15[CP15_FLUSH_PREFETCH_BUFFER] = value; } else if (crn == 7 && opcode_1 == 0 && crm == 10) { if (opcode_2 == 4) - cpu->CP15[CP15(CP15_DATA_SYNC_BARRIER)] = value; + cpu->CP15[CP15_DATA_SYNC_BARRIER] = value; else if (opcode_2 == 5) - cpu->CP15[CP15(CP15_DATA_MEMORY_BARRIER)] = value; + cpu->CP15[CP15_DATA_MEMORY_BARRIER] = value; } else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2) { - cpu->CP15[CP15(CP15_THREAD_UPRW)] = value; + cpu->CP15[CP15_THREAD_UPRW] = value; } } diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h index c232376e0..6c89774eb 100644 --- a/src/core/arm/skyeye_common/arm_regformat.h +++ b/src/core/arm/skyeye_common/arm_regformat.h @@ -51,17 +51,28 @@ enum { EXCLUSIVE_STATE, EXCLUSIVE_RESULT, + MAX_REG_NUM, +}; + +// VFP system registers +enum { + VFP_FPSID, + VFP_FPSCR, + VFP_FPEXC, + + // Not an actual register. + // All VFP system registers should be defined above this. + VFP_SYSTEM_REGISTER_COUNT +}; + +enum CP15Register { // c0 - Information registers - CP15_BASE, - CP15_C0 = CP15_BASE, - CP15_C0_C0 = CP15_C0, - CP15_MAIN_ID = CP15_C0_C0, + CP15_MAIN_ID, CP15_CACHE_TYPE, CP15_TCM_STATUS, CP15_TLB_TYPE, CP15_CPU_ID, - CP15_C0_C1, - CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1, + CP15_PROCESSOR_FEATURE_0, CP15_PROCESSOR_FEATURE_1, CP15_DEBUG_FEATURE_0, CP15_AUXILIARY_FEATURE_0, @@ -69,24 +80,19 @@ enum { CP15_MEMORY_MODEL_FEATURE_1, CP15_MEMORY_MODEL_FEATURE_2, CP15_MEMORY_MODEL_FEATURE_3, - CP15_C0_C2, - CP15_ISA_FEATURE_0 = CP15_C0_C2, + CP15_ISA_FEATURE_0, CP15_ISA_FEATURE_1, CP15_ISA_FEATURE_2, CP15_ISA_FEATURE_3, CP15_ISA_FEATURE_4, // c1 - Control registers - CP15_C1_C0, - CP15_CONTROL = CP15_C1_C0, + CP15_CONTROL, CP15_AUXILIARY_CONTROL, CP15_COPROCESSOR_ACCESS_CONTROL, // c2 - Translation table registers - CP15_C2, - CP15_C2_C0 = CP15_C2, - CP15_TRANSLATION_BASE = CP15_C2_C0, - CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE, + CP15_TRANSLATION_BASE_TABLE_0, CP15_TRANSLATION_BASE_TABLE_1, CP15_TRANSLATION_BASE_CONTROL, CP15_DOMAIN_ACCESS_CONTROL, @@ -171,14 +177,7 @@ enum { CP15_TLB_FAULT_ADDR, CP15_TLB_FAULT_STATUS, - // VFP registers - VFP_BASE, - VFP_FPSID = VFP_BASE, - VFP_FPSCR, - VFP_FPEXC, - - MAX_REG_NUM, + // Not an actual register. + // All registers should be defined above this. + CP15_REGISTER_COUNT, }; - -#define CP15(idx) (idx - CP15_BASE) -#define VFP_OFFSET(x) (x - VFP_BASE) diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h index d5b0242c3..743e935f0 100644 --- a/src/core/arm/skyeye_common/armdefs.h +++ b/src/core/arm/skyeye_common/armdefs.h @@ -91,14 +91,16 @@ struct ARMul_State ARMword exclusive_tag; // The address for which the local monitor is in exclusive access mode ARMword exclusive_state; ARMword exclusive_result; - ARMword CP15[VFP_BASE - CP15_BASE]; - ARMword VFP[3]; // FPSID, FPSCR, and FPEXC + ARMword CP15[CP15_REGISTER_COUNT]; + + // FPSID, FPSCR, and FPEXC + ARMword VFP[VFP_SYSTEM_REGISTER_COUNT]; // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), // and only 32 singleword registers are accessible (S0-S31). ARMword ExtReg[VFP_REG_NUM]; /* ---- End of the ordered registers ---- */ - + ARMword RegBank[7][16]; // all the registers ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed diff --git a/src/core/arm/skyeye_common/vfp/asm_vfp.h b/src/core/arm/skyeye_common/vfp/asm_vfp.h index ccb7cf4d7..1187924f4 100644 --- a/src/core/arm/skyeye_common/vfp/asm_vfp.h +++ b/src/core/arm/skyeye_common/vfp/asm_vfp.h @@ -7,15 +7,15 @@ #pragma once -// FPSID Information +// ARM11 MPCore FPSID Information // Note that these are used as values and not as flags. enum : u32 { - VFP_FPSID_IMPLMEN = 0, // Implementation code. Should be the same as cp15 0 c0 0 - VFP_FPSID_SW = 0, // Software emulation bit value - VFP_FPSID_SUBARCH = 0x2, // Subarchitecture version number - VFP_FPSID_PARTNUM = 0x1, // Part number - VFP_FPSID_VARIANT = 0x1, // Variant number - VFP_FPSID_REVISION = 0x1 // Revision number + VFP_FPSID_IMPLMEN = 0x41, // Implementation code. Should be the same as cp15 0 c0 0 + VFP_FPSID_SW = 0, // Software emulation bit value + VFP_FPSID_SUBARCH = 0x1, // Subarchitecture version number + VFP_FPSID_PARTNUM = 0x20, // Part number + VFP_FPSID_VARIANT = 0xB, // Variant number + VFP_FPSID_REVISION = 0x4 // Revision number }; // FPEXC bits diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp index 6286e7b62..d793261fd 100644 --- a/src/core/arm/skyeye_common/vfp/vfp.cpp +++ b/src/core/arm/skyeye_common/vfp/vfp.cpp @@ -29,10 +29,10 @@ unsigned VFPInit(ARMul_State* state) { - state->VFP[VFP_OFFSET(VFP_FPSID)] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 | - VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION; - state->VFP[VFP_OFFSET(VFP_FPEXC)] = 0; - state->VFP[VFP_OFFSET(VFP_FPSCR)] = 0; + state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 | + VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION; + state->VFP[VFP_FPEXC] = 0; + state->VFP[VFP_FPSCR] = 0; return 0; } @@ -314,11 +314,11 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr) int exceptions = 0; if (CoProc == 10) - exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]); + exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_FPSCR]); else - exceptions = vfp_double_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]); + exceptions = vfp_double_cpdo(state, instr, state->VFP[VFP_FPSCR]); - vfp_raise_exceptions(state, exceptions, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]); + vfp_raise_exceptions(state, exceptions, instr, state->VFP[VFP_FPSCR]); return ARMul_DONE; } @@ -344,11 +344,11 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value) { if (Rt != 15) { - *value = state->VFP[VFP_OFFSET(VFP_FPSCR)]; + *value = state->VFP[VFP_FPSCR]; } else { - *value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ; + *value = state->VFP[VFP_FPSCR] ; } } else @@ -356,7 +356,7 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value) switch (reg) { case 0: - *value = state->VFP[VFP_OFFSET(VFP_FPSID)]; + *value = state->VFP[VFP_FPSID]; break; case 6: /* MVFR1, VFPv3 only ? */ @@ -367,7 +367,7 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value) LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt); break; case 8: - *value = state->VFP[VFP_OFFSET(VFP_FPEXC)]; + *value = state->VFP[VFP_FPEXC]; break; default: LOG_TRACE(Core_ARM11, "\tSUBARCHITECTURE DEFINED\n"); @@ -407,11 +407,11 @@ void VMSR(ARMul_State* state, ARMword reg, ARMword Rt) { if (reg == 1) { - state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt]; + state->VFP[VFP_FPSCR] = state->Reg[Rt]; } else if (reg == 8) { - state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt]; + state->VFP[VFP_FPEXC] = state->Reg[Rt]; } } @@ -774,5 +774,5 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc fpscr |= exceptions; - state->VFP[VFP_OFFSET(VFP_FPSCR)] = fpscr; + state->VFP[VFP_FPSCR] = fpscr; } diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h index 445a224bc..1b72383e7 100644 --- a/src/core/arm/skyeye_common/vfp/vfp.h +++ b/src/core/arm/skyeye_common/vfp/vfp.h @@ -25,7 +25,7 @@ #define VFP_DEBUG_UNIMPLEMENTED(x) LOG_ERROR(Core_ARM11, "in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1); #define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested\n", __FUNCTION__); #define CHECK_VFP_ENABLED -#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);} +#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]); unsigned VFPInit(ARMul_State* state); unsigned VFPMRC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value); diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp index 368b5a25d..72afe2164 100644 --- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp +++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp @@ -46,9 +46,9 @@ VMLA_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -96,9 +96,9 @@ VMLS_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -146,9 +146,9 @@ VNMLA_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -197,9 +197,9 @@ VNMLS_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -247,9 +247,9 @@ VNMUL_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -297,9 +297,9 @@ VMUL_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -347,9 +347,9 @@ VADD_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -397,9 +397,9 @@ VSUB_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -447,9 +447,9 @@ VDIV_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -591,9 +591,9 @@ VABS_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -642,9 +642,9 @@ VNEG_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -692,9 +692,9 @@ VSQRT_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -742,9 +742,9 @@ VCMP_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -792,9 +792,9 @@ VCMP2_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -842,9 +842,9 @@ VCVTBDS_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -894,9 +894,9 @@ VCVTBFF_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -944,9 +944,9 @@ VCVTBFI_INST: int ret; if (inst_cream->dp_operation) - ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); else - ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); + ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]); CHECK_VFP_CDP_RET; } @@ -1146,14 +1146,14 @@ VMRS_INST: { if (inst_cream->Rt != 15) { - cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSCR)]; + cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSCR]; } else { - cpu->NFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 31) & 1; - cpu->ZFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 30) & 1; - cpu->CFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 29) & 1; - cpu->VFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 28) & 1; + cpu->NFlag = (cpu->VFP[VFP_FPSCR] >> 31) & 1; + cpu->ZFlag = (cpu->VFP[VFP_FPSCR] >> 30) & 1; + cpu->CFlag = (cpu->VFP[VFP_FPSCR] >> 29) & 1; + cpu->VFlag = (cpu->VFP[VFP_FPSCR] >> 28) & 1; } } else @@ -1161,7 +1161,7 @@ VMRS_INST: switch (inst_cream->reg) { case 0: - cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSID)]; + cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSID]; break; case 6: /* MVFR1, VFPv3 only ? */ @@ -1172,7 +1172,7 @@ VMRS_INST: LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", inst_cream->Rt); break; case 8: - cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPEXC)]; + cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPEXC]; break; default: break; diff --git a/src/core/core.cpp b/src/core/core.cpp index 15787bc17..81e642318 100644 --- a/src/core/core.cpp +++ b/src/core/core.cpp @@ -7,6 +7,7 @@ #include "core/core.h" #include "core/core_timing.h" +#include "core/mem_map.h" #include "core/settings.h" #include "core/arm/arm_interface.h" #include "core/arm/disassembler/arm_disasm.h" @@ -59,6 +60,10 @@ int Init() { g_sys_core = new ARM_DynCom(USER32MODE); g_app_core = new ARM_DynCom(USER32MODE); + // TODO: Whenever TLS is implemented, this should contain + // the address of the 0x200-byte TLS + g_app_core->SetCP15Register(CP15_THREAD_URO, Memory::KERNEL_MEMORY_VADDR); + LOG_DEBUG(Core, "Initialized OK"); return 0; } diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp index 26d3bcff6..8da063bd2 100644 --- a/src/core/hle/service/gsp_gpu.cpp +++ b/src/core/hle/service/gsp_gpu.cpp @@ -204,16 +204,18 @@ static void ReadHWRegs(Service::Interface* self) { static void SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) { u32 base_address = 0x400000; + PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left); + PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right); if (info.active_fb == 0) { WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)), 4, - &info.address_left); + &phys_address_left); WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)), 4, - &info.address_right); + &phys_address_right); } else { WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)), 4, - &info.address_left); + &phys_address_left); WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)), 4, - &info.address_right); + &phys_address_right); } WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)), 4, &info.stride); diff --git a/src/core/mem_map.h b/src/core/mem_map.h index bce99dffa..ff730593e 100644 --- a/src/core/mem_map.h +++ b/src/core/mem_map.h @@ -27,10 +27,16 @@ enum : u32 { MPCORE_PRIV_PADDR_END = (MPCORE_PRIV_PADDR + MPCORE_PRIV_SIZE), FCRAM_SIZE = 0x08000000, ///< FCRAM size - FCRAM_PADDR = 0x20000000, ///< FCRAM physical address - FCRAM_PADDR_END = (FCRAM_PADDR + FCRAM_SIZE), ///< FCRAM end of physical space - FCRAM_VADDR = 0x08000000, ///< FCRAM virtual address - FCRAM_VADDR_END = (FCRAM_VADDR + FCRAM_SIZE), ///< FCRAM end of virtual space + FCRAM_PADDR = 0x20000000, ///< FCRAM physical address + FCRAM_PADDR_END = (FCRAM_PADDR + FCRAM_SIZE), + + HEAP_SIZE = FCRAM_SIZE, ///< Application heap size + HEAP_VADDR = 0x08000000, + HEAP_VADDR_END = (HEAP_VADDR + HEAP_SIZE), + + HEAP_LINEAR_SIZE = FCRAM_SIZE, + HEAP_LINEAR_VADDR = 0x14000000, + HEAP_LINEAR_VADDR_END = (HEAP_LINEAR_VADDR + HEAP_LINEAR_SIZE), AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size AXI_WRAM_PADDR = 0x1FF80000, ///< AXI WRAM physical address @@ -65,18 +71,6 @@ enum : u32 { SYSTEM_MEMORY_VADDR = 0x04000000, SYSTEM_MEMORY_VADDR_END = (SYSTEM_MEMORY_VADDR + SYSTEM_MEMORY_SIZE), - HEAP_SIZE = FCRAM_SIZE, ///< Application heap size - //HEAP_PADDR = HEAP_GSP_SIZE, - //HEAP_PADDR_END = (HEAP_PADDR + HEAP_SIZE), - HEAP_VADDR = 0x08000000, - HEAP_VADDR_END = (HEAP_VADDR + HEAP_SIZE), - - HEAP_LINEAR_SIZE = 0x08000000, ///< Linear heap size... TODO: Define correctly? - HEAP_LINEAR_VADDR = 0x14000000, - HEAP_LINEAR_VADDR_END = (HEAP_LINEAR_VADDR + HEAP_LINEAR_SIZE), - HEAP_LINEAR_PADDR = 0x00000000, - HEAP_LINEAR_PADDR_END = (HEAP_LINEAR_PADDR + HEAP_LINEAR_SIZE), - HARDWARE_IO_SIZE = 0x01000000, HARDWARE_IO_PADDR = 0x10000000, ///< IO physical address start HARDWARE_IO_VADDR = 0x1EC00000, ///< IO virtual address start diff --git a/src/core/mem_map_funcs.cpp b/src/core/mem_map_funcs.cpp index a161a8204..5878b99dc 100644 --- a/src/core/mem_map_funcs.cpp +++ b/src/core/mem_map_funcs.cpp @@ -23,10 +23,12 @@ VAddr PhysicalToVirtualAddress(const PAddr addr) { // to virtual address translations here. This is quite hacky, but necessary until we implement // proper MMU emulation. // TODO: Screw it, I'll let bunnei figure out how to do this properly. - if ((addr >= VRAM_PADDR) && (addr < VRAM_PADDR_END)) { + if (addr == 0) { + return 0; + } else if ((addr >= VRAM_PADDR) && (addr < VRAM_PADDR_END)) { return addr - VRAM_PADDR + VRAM_VADDR; - }else if ((addr >= FCRAM_PADDR) && (addr < FCRAM_PADDR_END)) { - return addr - FCRAM_PADDR + FCRAM_VADDR; + } else if ((addr >= FCRAM_PADDR) && (addr < FCRAM_PADDR_END)) { + return addr - FCRAM_PADDR + HEAP_LINEAR_VADDR; } LOG_ERROR(HW_Memory, "Unknown physical address @ 0x%08x", addr); @@ -39,10 +41,12 @@ PAddr VirtualToPhysicalAddress(const VAddr addr) { // to virtual address translations here. This is quite hacky, but necessary until we implement // proper MMU emulation. // TODO: Screw it, I'll let bunnei figure out how to do this properly. - if ((addr >= VRAM_VADDR) && (addr < VRAM_VADDR_END)) { - return addr - 0x07000000; - } else if ((addr >= FCRAM_VADDR) && (addr < FCRAM_VADDR_END)) { - return addr - FCRAM_VADDR + FCRAM_PADDR; + if (addr == 0) { + return 0; + } else if ((addr >= VRAM_VADDR) && (addr < VRAM_VADDR_END)) { + return addr - VRAM_VADDR + VRAM_PADDR; + } else if ((addr >= HEAP_LINEAR_VADDR) && (addr < HEAP_LINEAR_VADDR_END)) { + return addr - HEAP_LINEAR_VADDR + FCRAM_PADDR; } LOG_ERROR(HW_Memory, "Unknown virtual address @ 0x%08x", addr); diff --git a/src/core/settings.h b/src/core/settings.h index 870eea958..0f4700241 100644 --- a/src/core/settings.h +++ b/src/core/settings.h @@ -44,6 +44,11 @@ struct Values { // System Region int region_value; + // Renderer + float bg_red; + float bg_green; + float bg_blue; + std::string log_filter; } extern values; diff --git a/src/video_core/debug_utils/debug_utils.cpp b/src/video_core/debug_utils/debug_utils.cpp index 83982b4f2..c460146cb 100644 --- a/src/video_core/debug_utils/debug_utils.cpp +++ b/src/video_core/debug_utils/debug_utils.cpp @@ -597,7 +597,7 @@ void DumpTexture(const Pica::Regs::TextureConfig& texture_config, u8* data) { png_init_io(png_ptr, fp.GetHandle()); - // Write header (8 bit colour depth) + // Write header (8 bit color depth) png_set_IHDR(png_ptr, info_ptr, texture_config.width, texture_config.height, 8, PNG_COLOR_TYPE_RGB /*_ALPHA*/, PNG_INTERLACE_NONE, PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); diff --git a/src/video_core/renderer_opengl/renderer_opengl.cpp b/src/video_core/renderer_opengl/renderer_opengl.cpp index 4273a177f..5e864b75e 100644 --- a/src/video_core/renderer_opengl/renderer_opengl.cpp +++ b/src/video_core/renderer_opengl/renderer_opengl.cpp @@ -6,6 +6,7 @@ #include "core/hw/hw.h" #include "core/hw/lcd.h" #include "core/mem_map.h" +#include "core/settings.h" #include "common/emu_window.h" #include "common/profiler_reporting.h" @@ -172,7 +173,7 @@ void RendererOpenGL::LoadColorToActiveGLTexture(u8 color_r, u8 color_g, u8 color * Initializes the OpenGL state and creates persistent objects. */ void RendererOpenGL::InitOpenGLObjects() { - glClearColor(1.0f, 1.0f, 1.0f, 0.0f); + glClearColor(Settings::values.bg_red, Settings::values.bg_green, Settings::values.bg_blue, 0.0f); glDisable(GL_DEPTH_TEST); // Link shaders and get variable locations diff --git a/src/video_core/utils.h b/src/video_core/utils.h index bda793fa5..ffb3e73a3 100644 --- a/src/video_core/utils.h +++ b/src/video_core/utils.h @@ -13,10 +13,10 @@ namespace VideoCore { /// Structure for the TGA texture format (for dumping) struct TGAHeader { char idlength; - char colourmaptype; + char colormaptype; char datatypecode; - short int colourmaporigin; - short int colourmaplength; + short int colormaporigin; + short int colormaplength; short int x_origin; short int y_origin; short width; |