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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp80
1 files changed, 34 insertions, 46 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index d8a708b9e..d953adba9 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -9,6 +9,7 @@
#include <unordered_map>
#include "common/logging/log.h"
+#include "common/profiler.h"
#include "core/mem_map.h"
#include "core/hle/hle.h"
@@ -20,6 +21,9 @@
#include "core/arm/skyeye_common/armmmu.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
+Common::Profiling::TimingCategory profile_execute("DynCom::Execute");
+Common::Profiling::TimingCategory profile_decode("DynCom::Decode");
+
enum {
COND = (1 << 0),
NON_BRANCH = (1 << 1),
@@ -3569,6 +3573,8 @@ typedef struct instruction_set_encoding_item ISEITEM;
extern const ISEITEM arm_instruction[];
static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, addr_t addr) {
+ Common::Profiling::ScopeTimer timer_decode(profile_decode);
+
// Decode instruction, get index
// Allocate memory and init InsCream
// Go on next, until terminal instruction
@@ -3641,6 +3647,8 @@ static bool InAPrivilegedMode(ARMul_State* core) {
}
unsigned InterpreterMainLoop(ARMul_State* state) {
+ Common::Profiling::ScopeTimer timer_execute(profile_execute);
+
#undef RM
#undef RS
@@ -4354,6 +4362,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
cpu->Reg[14] = Memory::Read32(addr);
else
cpu->Reg_usr[1] = Memory::Read32(addr);
+
+ addr += 4;
}
} else if (!BIT(inst, 22)) {
for(int i = 0; i < 16; i++ ){
@@ -4478,10 +4488,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
RD = RN + operand2;
- if (inst_cream->Rn == 15 || inst_cream->Rm == 15) {
- LOG_ERROR(Core_ARM11, "invalid operands for UXTAH");
- CITRA_IGNORE_EXIT(-1);
- }
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(uxtah_inst));
@@ -4812,10 +4818,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
uint64_t rm = RM;
uint64_t rs = RS;
uint64_t rn = RN;
- if (inst_cream->Rm == 15 || inst_cream->Rs == 15 || inst_cream->Rn == 15) {
- LOG_ERROR(Core_ARM11, "invalid operands for MLA");
- CITRA_IGNORE_EXIT(-1);
- }
+
RD = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff);
if (inst_cream->S) {
UPDATE_NFLAG(RD);
@@ -5094,10 +5097,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
PLD_INST:
{
- // Instruction not implemented
- //LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
+ // Not implemented. PLD is a hint instruction, so it's optional.
+
cpu->Reg[15] += GET_INST_SIZE(cpu);
- INC_PC(sizeof(stc_inst));
+ INC_PC(sizeof(pld_inst));
FETCH_INST;
GOTO_NEXT_INST;
}
@@ -5966,54 +5969,51 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
unsigned int inst = inst_cream->inst;
- int i;
unsigned int Rn = BITS(inst, 16, 19);
unsigned int old_RN = cpu->Reg[Rn];
inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
if (BIT(inst_cream->inst, 22) == 1) {
- for (i = 0; i < 13; i++) {
- if(BIT(inst_cream->inst, i)) {
+ for (int i = 0; i < 13; i++) {
+ if (BIT(inst_cream->inst, i)) {
Memory::Write32(addr, cpu->Reg[i]);
addr += 4;
}
}
if (BIT(inst_cream->inst, 13)) {
- if (cpu->Mode == USER32MODE) {
- Memory::Write32(addr, cpu->Reg[i]);
- addr += 4;
- } else {
+ if (cpu->Mode == USER32MODE)
+ Memory::Write32(addr, cpu->Reg[13]);
+ else
Memory::Write32(addr, cpu->Reg_usr[0]);
- addr += 4;
- }
+
+ addr += 4;
}
if (BIT(inst_cream->inst, 14)) {
- if (cpu->Mode == USER32MODE) {
- Memory::Write32(addr, cpu->Reg[i]);
- addr += 4;
- } else {
+ if (cpu->Mode == USER32MODE)
+ Memory::Write32(addr, cpu->Reg[14]);
+ else
Memory::Write32(addr, cpu->Reg_usr[1]);
- addr += 4;
- }
+
+ addr += 4;
}
if (BIT(inst_cream->inst, 15)) {
Memory::Write32(addr, cpu->Reg_usr[1] + 8);
}
} else {
- for( i = 0; i < 15; i++ ) {
- if(BIT(inst_cream->inst, i)) {
- if(i == Rn)
+ for (int i = 0; i < 15; i++) {
+ if (BIT(inst_cream->inst, i)) {
+ if (i == Rn)
Memory::Write32(addr, old_RN);
else
Memory::Write32(addr, cpu->Reg[i]);
+
addr += 4;
}
}
// Check PC reg
- if(BIT(inst_cream->inst, i)) {
+ if (BIT(inst_cream->inst, 15))
Memory::Write32(addr, cpu->Reg_usr[1] + 8);
- }
}
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -6026,15 +6026,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component;
- if (inst_cream->Rm == 15) {
- LOG_ERROR(Core_ARM11, "invalid operand for SXTB");
- CITRA_IGNORE_EXIT(-1);
- }
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
if (BIT(operand2, 7)) {
operand2 |= 0xffffff00;
- } else
+ } else {
operand2 &= 0xff;
+ }
RD = operand2;
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -6292,8 +6289,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
swp_inst* inst_cream = (swp_inst*)inst_base->component;
addr = RN;
- unsigned int value;
- value = Memory::Read32(addr);
+ unsigned int value = Memory::Read32(addr);
Memory::Write32(addr, RM);
RD = value;
@@ -6322,10 +6318,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component;
- // R15 should be check
- if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15){
- CITRA_IGNORE_EXIT(-1);
- }
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
// Sign extend for byte
@@ -6376,10 +6368,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component;
- // R15 should be check
- if(inst_cream->Rn == 15 || inst_cream->Rm == 15 || inst_cream->Rd ==15) {
- CITRA_IGNORE_EXIT(-1);
- }
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
// Sign extend for half
operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 03:52:36 +0100