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-rw-r--r--src/video_core/engines/fermi_2d.h14
-rw-r--r--src/video_core/engines/maxwell_3d.h41
-rw-r--r--src/video_core/engines/shader_bytecode.h148
3 files changed, 198 insertions, 5 deletions
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 81d15c62a..2a6e8bbbb 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -36,9 +36,9 @@ public:
RenderTargetFormat format;
BitField<0, 1, u32> linear;
union {
- BitField<0, 4, u32> block_depth;
+ BitField<0, 4, u32> block_width;
BitField<4, 4, u32> block_height;
- BitField<8, 4, u32> block_width;
+ BitField<8, 4, u32> block_depth;
};
u32 depth;
u32 layer;
@@ -53,10 +53,20 @@ public:
address_low);
}
+ u32 BlockWidth() const {
+ // The block width is stored in log2 format.
+ return 1 << block_width;
+ }
+
u32 BlockHeight() const {
// The block height is stored in log2 format.
return 1 << block_height;
}
+
+ u32 BlockDepth() const {
+ // The block depth is stored in log2 format.
+ return 1 << block_depth;
+ }
};
static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 4290da33f..c8d1b6478 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -347,6 +347,16 @@ public:
DecrWrap = 8,
};
+ enum class MemoryLayout : u32 {
+ Linear = 0,
+ BlockLinear = 1,
+ };
+
+ enum class InvMemoryLayout : u32 {
+ BlockLinear = 0,
+ Linear = 1,
+ };
+
struct Cull {
enum class FrontFace : u32 {
ClockWise = 0x0900,
@@ -432,7 +442,12 @@ public:
u32 width;
u32 height;
Tegra::RenderTargetFormat format;
- u32 block_dimensions;
+ union {
+ BitField<0, 3, u32> block_width;
+ BitField<4, 3, u32> block_height;
+ BitField<8, 3, u32> block_depth;
+ BitField<12, 1, InvMemoryLayout> type;
+ } memory_layout;
u32 array_mode;
u32 layer_stride;
u32 base_layer;
@@ -532,7 +547,21 @@ public:
INSERT_PADDING_WORDS(0x3);
s32 clear_stencil;
- INSERT_PADDING_WORDS(0x6C);
+ INSERT_PADDING_WORDS(0x17);
+
+ struct {
+ u32 enable;
+ union {
+ BitField<0, 16, u32> min_x;
+ BitField<16, 16, u32> max_x;
+ };
+ union {
+ BitField<0, 16, u32> min_y;
+ BitField<16, 16, u32> max_y;
+ };
+ } scissor_test;
+
+ INSERT_PADDING_WORDS(0x52);
s32 stencil_back_func_ref;
u32 stencil_back_mask;
@@ -548,7 +577,12 @@ public:
u32 address_high;
u32 address_low;
Tegra::DepthFormat format;
- u32 block_dimensions;
+ union {
+ BitField<0, 4, u32> block_width;
+ BitField<4, 4, u32> block_height;
+ BitField<8, 4, u32> block_depth;
+ BitField<20, 1, InvMemoryLayout> type;
+ } memory_layout;
u32 layer_stride;
GPUVAddr Address() const {
@@ -1002,6 +1036,7 @@ ASSERT_REG_POSITION(vertex_buffer, 0x35D);
ASSERT_REG_POSITION(clear_color[0], 0x360);
ASSERT_REG_POSITION(clear_depth, 0x364);
ASSERT_REG_POSITION(clear_stencil, 0x368);
+ASSERT_REG_POSITION(scissor_test, 0x380);
ASSERT_REG_POSITION(stencil_back_func_ref, 0x3D5);
ASSERT_REG_POSITION(stencil_back_mask, 0x3D6);
ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D7);
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index b1f137b9c..9a59b65b3 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -214,6 +214,18 @@ enum class IMinMaxExchange : u64 {
XHi = 3,
};
+enum class VmadType : u64 {
+ Size16_Low = 0,
+ Size16_High = 1,
+ Size32 = 2,
+ Invalid = 3,
+};
+
+enum class VmadShr : u64 {
+ Shr7 = 1,
+ Shr15 = 2,
+};
+
enum class XmadMode : u64 {
None = 0,
CLo = 1,
@@ -314,6 +326,15 @@ enum class TextureMiscMode : u64 {
PTP,
};
+enum class IsberdMode : u64 {
+ None = 0,
+ Patch = 1,
+ Prim = 2,
+ Attr = 3,
+};
+
+enum class IsberdShift : u64 { None = 0, U16 = 1, B32 = 2 };
+
enum class IpaInterpMode : u64 {
Linear = 0,
Perspective = 1,
@@ -340,6 +361,87 @@ struct IpaMode {
}
};
+enum class SystemVariable : u64 {
+ LaneId = 0x00,
+ VirtCfg = 0x02,
+ VirtId = 0x03,
+ Pm0 = 0x04,
+ Pm1 = 0x05,
+ Pm2 = 0x06,
+ Pm3 = 0x07,
+ Pm4 = 0x08,
+ Pm5 = 0x09,
+ Pm6 = 0x0a,
+ Pm7 = 0x0b,
+ OrderingTicket = 0x0f,
+ PrimType = 0x10,
+ InvocationId = 0x11,
+ Ydirection = 0x12,
+ ThreadKill = 0x13,
+ ShaderType = 0x14,
+ DirectBeWriteAddressLow = 0x15,
+ DirectBeWriteAddressHigh = 0x16,
+ DirectBeWriteEnabled = 0x17,
+ MachineId0 = 0x18,
+ MachineId1 = 0x19,
+ MachineId2 = 0x1a,
+ MachineId3 = 0x1b,
+ Affinity = 0x1c,
+ InvocationInfo = 0x1d,
+ WscaleFactorXY = 0x1e,
+ WscaleFactorZ = 0x1f,
+ Tid = 0x20,
+ TidX = 0x21,
+ TidY = 0x22,
+ TidZ = 0x23,
+ CtaParam = 0x24,
+ CtaIdX = 0x25,
+ CtaIdY = 0x26,
+ CtaIdZ = 0x27,
+ NtId = 0x28,
+ CirQueueIncrMinusOne = 0x29,
+ Nlatc = 0x2a,
+ SmSpaVersion = 0x2c,
+ MultiPassShaderInfo = 0x2d,
+ LwinHi = 0x2e,
+ SwinHi = 0x2f,
+ SwinLo = 0x30,
+ SwinSz = 0x31,
+ SmemSz = 0x32,
+ SmemBanks = 0x33,
+ LwinLo = 0x34,
+ LwinSz = 0x35,
+ LmemLosz = 0x36,
+ LmemHioff = 0x37,
+ EqMask = 0x38,
+ LtMask = 0x39,
+ LeMask = 0x3a,
+ GtMask = 0x3b,
+ GeMask = 0x3c,
+ RegAlloc = 0x3d,
+ CtxAddr = 0x3e, // .fmask = F_SM50
+ BarrierAlloc = 0x3e, // .fmask = F_SM60
+ GlobalErrorStatus = 0x40,
+ WarpErrorStatus = 0x42,
+ WarpErrorStatusClear = 0x43,
+ PmHi0 = 0x48,
+ PmHi1 = 0x49,
+ PmHi2 = 0x4a,
+ PmHi3 = 0x4b,
+ PmHi4 = 0x4c,
+ PmHi5 = 0x4d,
+ PmHi6 = 0x4e,
+ PmHi7 = 0x4f,
+ ClockLo = 0x50,
+ ClockHi = 0x51,
+ GlobalTimerLo = 0x52,
+ GlobalTimerHi = 0x53,
+ HwTaskId = 0x60,
+ CircularQueueEntryIndex = 0x61,
+ CircularQueueEntryAddressLow = 0x62,
+ CircularQueueEntryAddressHigh = 0x63,
+};
+
union Instruction {
Instruction& operator=(const Instruction& instr) {
value = instr.value;
@@ -362,6 +464,7 @@ union Instruction {
BitField<48, 16, u64> opcode;
union {
+ BitField<20, 16, u64> imm20_16;
BitField<20, 19, u64> imm20_19;
BitField<20, 32, s64> imm20_32;
BitField<45, 1, u64> negate_b;
@@ -403,6 +506,10 @@ union Instruction {
}
} lop3;
+ u16 GetImm20_16() const {
+ return static_cast<u16>(imm20_16);
+ }
+
u32 GetImm20_19() const {
u32 imm{static_cast<u32>(imm20_19)};
imm <<= 12;
@@ -915,6 +1022,35 @@ union Instruction {
} bra;
union {
+ BitField<39, 1, u64> emit; // EmitVertex
+ BitField<40, 1, u64> cut; // EndPrimitive
+ } out;
+
+ union {
+ BitField<31, 1, u64> skew;
+ BitField<32, 1, u64> o;
+ BitField<33, 2, IsberdMode> mode;
+ BitField<47, 2, IsberdShift> shift;
+ } isberd;
+
+ union {
+ BitField<48, 1, u64> signed_a;
+ BitField<38, 1, u64> is_byte_chunk_a;
+ BitField<36, 2, VmadType> type_a;
+ BitField<36, 2, u64> byte_height_a;
+
+ BitField<49, 1, u64> signed_b;
+ BitField<50, 1, u64> use_register_b;
+ BitField<30, 1, u64> is_byte_chunk_b;
+ BitField<28, 2, VmadType> type_b;
+ BitField<28, 2, u64> byte_height_b;
+
+ BitField<51, 2, VmadShr> shr;
+ BitField<55, 1, u64> saturate; // Saturates the result (a * b + c)
+ BitField<47, 1, u64> cc;
+ } vmad;
+
+ union {
BitField<20, 16, u64> imm20_16;
BitField<36, 1, u64> product_shift_left;
BitField<37, 1, u64> merge_37;
@@ -936,6 +1072,10 @@ union Instruction {
BitField<36, 5, u64> index;
} cbuf36;
+ // Unsure about the size of this one.
+ // It's always used with a gpr0, so any size should be fine.
+ BitField<20, 8, SystemVariable> sys20;
+
BitField<47, 1, u64> generates_cc;
BitField<61, 1, u64> is_b_imm;
BitField<60, 1, u64> is_b_gpr;
@@ -975,6 +1115,9 @@ public:
TMML, // Texture Mip Map Level
EXIT,
IPA,
+ OUT_R, // Emit vertex/primitive
+ ISBERD,
+ VMAD,
FFMA_IMM, // Fused Multiply and Add
FFMA_CR,
FFMA_RC,
@@ -1034,6 +1177,7 @@ public:
MOV_C,
MOV_R,
MOV_IMM,
+ MOV_SYS,
MOV32_IMM,
SHL_C,
SHL_R,
@@ -1209,6 +1353,9 @@ private:
INST("1101111101011---", Id::TMML, Type::Memory, "TMML"),
INST("111000110000----", Id::EXIT, Type::Trivial, "EXIT"),
INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
+ INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
+ INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
+ INST("01011111--------", Id::VMAD, Type::Trivial, "VMAD"),
INST("0011001-1-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
@@ -1255,6 +1402,7 @@ private:
INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
+ INST("1111000011001---", Id::MOV_SYS, Type::Trivial, "MOV_SYS"),
INST("000000010000----", Id::MOV32_IMM, Type::ArithmeticImmediate, "MOV32_IMM"),
INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 19:39:06 +0100