summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSubv <subv2112@gmail.com>2018-04-20 16:16:55 +0200
committerSubv <subv2112@gmail.com>2018-04-21 04:09:33 +0200
commitc3a8ea76f180fbaf2d58d0454e7adc2bb1f30009 (patch)
tree5b23e8812808e3b3f87a874b0d4e5a418675ea85
parentShaderGen: Implemented the fsetp instruction. (diff)
downloadyuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.tar
yuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.tar.gz
yuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.tar.bz2
yuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.tar.lz
yuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.tar.xz
yuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.tar.zst
yuzu-c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009.zip
Diffstat (limited to '')
-rw-r--r--src/video_core/engines/shader_bytecode.h6
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp35
2 files changed, 40 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index fb639a417..e6c2fd367 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -331,7 +331,11 @@ union Instruction {
OpCode opcode;
BitField<0, 8, Register> gpr0;
BitField<8, 8, Register> gpr8;
- BitField<16, 4, Pred> pred;
+ union {
+ BitField<16, 4, Pred> full_pred;
+ BitField<16, 3, u64> pred_index;
+ } pred;
+ BitField<19, 1, u64> negate_pred;
BitField<20, 8, Register> gpr20;
BitField<20, 7, SubOp> sub_op;
BitField<28, 8, Register> gpr28;
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 2e0203a68..7aaee9464 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -294,6 +294,25 @@ private:
}
/*
+ * Returns the condition to use in the 'if' for a predicated instruction.
+ * @param instr Instruction to generate the if condition for.
+ * @returns string containing the predicate condition.
+ */
+ std::string GetPredicateCondition(Instruction instr) const {
+ using Tegra::Shader::Pred;
+ ASSERT(instr.pred.pred_index != static_cast<u64>(Pred::UnusedIndex));
+
+ std::string variable =
+ 'p' + std::to_string(static_cast<u64>(instr.pred.pred_index.Value()));
+
+ if (instr.negate_pred) {
+ return "!(" + variable + ')';
+ }
+
+ return variable;
+ }
+
+ /*
* Returns whether the instruction at the specified offset is a 'sched' instruction.
* Sched instructions always appear before a sequence of 3 instructions.
*/
@@ -320,6 +339,16 @@ private:
shader.AddLine("// " + std::to_string(offset) + ": " + OpCode::GetInfo(instr.opcode).name);
+ using Tegra::Shader::Pred;
+ ASSERT_MSG(instr.pred.full_pred != Pred::NeverExecute,
+ "NeverExecute predicate not implemented");
+
+ if (instr.pred.pred_index != static_cast<u64>(Pred::UnusedIndex)) {
+ shader.AddLine("if (" + GetPredicateCondition(instr) + ')');
+ shader.AddLine('{');
+ ++shader.scope;
+ }
+
switch (OpCode::GetInfo(instr.opcode).type) {
case OpCode::Type::Arithmetic: {
std::string dest = GetRegister(instr.gpr0);
@@ -559,6 +588,12 @@ private:
}
}
+ // Close the predicate condition scope.
+ if (instr.pred != Pred::UnusedIndex) {
+ --shader.scope;
+ shader.AddLine('}');
+ }
+
return offset + 1;
}