2 files changed, 109 insertions, 14 deletions

diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 5d174a08f..551bb77a6 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -28,9 +28,40 @@
 #include "core/arm/dyncom/arm_dyncom_dec.h"
 
 const ISEITEM arm_instruction[] = {
-	#define VFP_DECODE
-	#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
-	#undef VFP_DECODE
+	{"vmla",        4,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x0,    9, 11, 0x5,     4, 4, 0},
+	{"vmls",        7,      ARMVFP2,        28, 31, 0xF,   25, 27, 0x1,   23, 23, 1,  11, 11, 0,  8, 9, 0x2,  6, 6, 1,  4, 4, 0},
+	{"vnmla",       4,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x1,    9, 11, 0x5,     4, 4, 0},
+	{"vnmla",       5,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x2,    9, 11, 0x5,     6, 6, 1,     4, 4, 0},
+	{"vnmls",       5,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x1,    9, 11, 0x5,     6, 6, 0,     4, 4, 0},
+	{"vnmul",       5,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x2,    9, 11, 0x5,     6, 6, 1,     4, 4, 0},
+	{"vmul",        5,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x2,    9, 11, 0x5,     6, 6, 0,     4, 4, 0},
+	{"vadd",        5,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x3,    9, 11, 0x5,     6, 6, 0,     4, 4, 0},
+	{"vsub",        5,      ARMVFP2,        23, 27, 0x1C,  20, 21, 0x3,    9, 11, 0x5,     6, 6, 1,     4, 4, 0},
+	{"vdiv",        5,      ARMVFP2,        23, 27, 0x1D,  20, 21, 0x0,    9, 11, 0x5,     6, 6, 0,     4, 4, 0},
+	{"vmov(i)",     4,      ARMVFP3,        23, 27, 0x1D,  20, 21, 0x3,    9, 11, 0x5,     4, 7, 0},
+	{"vmov(r)",     5,      ARMVFP3,        23, 27, 0x1D,  16, 21, 0x30,   9, 11, 0x5,     6, 7, 1,     4, 4, 0},
+	{"vabs",        5,      ARMVFP2,        23, 27, 0x1D,  16, 21, 0x30,   9, 11, 0x5,     6, 7, 3,     4, 4, 0},
+	{"vneg",        5,      ARMVFP2,        23, 27, 0x1D,  17, 21, 0x18,   9, 11, 0x5,     6, 7, 1,     4, 4, 0},
+	{"vsqrt",       5,      ARMVFP2,        23, 27, 0x1D,  16, 21, 0x31,   9, 11, 0x5,     6, 7, 3,     4, 4, 0},
+	{"vcmp",        5,      ARMVFP2,        23, 27, 0x1D,  16, 21, 0x34,   9, 11, 0x5,     6, 6, 1,     4, 4, 0},
+	{"vcmp2",       5,      ARMVFP2,        23, 27, 0x1D,  16, 21, 0x35,   9, 11, 0x5,     0, 6, 0x40},
+	{"vcvt(bds)",   5,      ARMVFP2,        23, 27, 0x1D,  16, 21, 0x37,   9, 11, 0x5,     6, 7, 3,     4, 4, 0},
+	{"vcvt(bff)",   6,      ARMVFP3,        23, 27, 0x1D,  19, 21, 0x7,    17, 17, 0x1,    9, 11,5,     6, 6, 1},
+	{"vcvt(bfi)",   5,      ARMVFP2,        23, 27, 0x1D,  19, 21, 0x7,    9, 11, 0x5,     6, 6, 1,     4, 4, 0},
+	{"vmovbrs",     3,      ARMVFP2,        21, 27, 0x70,   8, 11, 0xA,    0, 6, 0x10},
+	{"vmsr",        2,      ARMVFP2,        20, 27, 0xEE,   0, 11, 0xA10},
+	{"vmovbrc",     4,      ARMVFP2,        23, 27, 0x1C,   20, 20, 0x0,   8, 11, 0xB,     0,4,0x10},
+	{"vmrs",        2,      ARMVFP2,        20, 27, 0xEF,   0, 11, 0xA10},
+	{"vmovbcr",     4,      ARMVFP2,        24, 27, 0xE,    20, 20, 1,     8, 11, 0xB,     0,4,0x10},
+	{"vmovbrrss",   3,      ARMVFP2,        21, 27, 0x62,   8, 11, 0xA,    4, 4, 1},
+	{"vmovbrrd",    3,      ARMVFP2,        21, 27, 0x62,   6, 11, 0x2C,   4, 4, 1},
+	{"vstr",        3,      ARMVFP2,        24, 27, 0xD,    20, 21, 0,     9, 11,5},
+	{"vpush",       3,      ARMVFP2,        23, 27, 0x1A,   16, 21, 0x2D,  9, 11,5},
+	{"vstm",        3,      ARMVFP2,        25, 27, 0x6,    20, 20, 0,     9, 11,5},
+	{"vpop",        3,      ARMVFP2,        23, 27, 0x19,   16, 21, 0x3D,  9, 11,5},
+	{"vldr",        3,      ARMVFP2,        24, 27, 0xD,    20, 21, 1,     9, 11,5},
+	{"vldm",        3,      ARMVFP2,        25, 27, 0x6,    20, 20, 1,     9, 11,5},
+
 	{"srs"	,  4	,  6	, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d,  8, 11, 0x00000005},
 	{"rfe"	,  4	,  6	, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001,  8, 11, 0x0000000a},
 	{"bkpt"	,  2	,  3	, 20, 31, 0x00000e12,  4,  7, 0x00000007},
@@ -187,9 +218,40 @@ const ISEITEM arm_instruction[] = {
 };
 
 const ISEITEM arm_exclusion_code[] = {
-	#define VFP_DECODE_EXCLUSION
-	#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
-	#undef VFP_DECODE_EXCLUSION
+	{"vmla",        0,      ARMVFP2, 0},
+	{"vmls",        0,      ARMVFP2, 0},
+	{"vnmla",       0,      ARMVFP2, 0},
+	{"vnmla",       0,      ARMVFP2, 0},
+	{"vnmls",       0,      ARMVFP2, 0},
+	{"vnmul",       0,      ARMVFP2, 0},
+	{"vmul",        0,      ARMVFP2, 0},
+	{"vadd",        0,      ARMVFP2, 0},
+	{"vsub",        0,      ARMVFP2, 0},
+	{"vdiv",        0,      ARMVFP2, 0},
+	{"vmov(i)",     0,      ARMVFP3, 0},
+	{"vmov(r)",     0,      ARMVFP3, 0},
+	{"vabs",        0,      ARMVFP2, 0},
+	{"vneg",        0,      ARMVFP2, 0},
+	{"vsqrt",       0,      ARMVFP2, 0},
+	{"vcmp",        0,      ARMVFP2, 0},
+	{"vcmp2",       0,      ARMVFP2, 0},
+	{"vcvt(bff)",   0,      ARMVFP3,         4, 4, 1},
+	{"vcvt(bds)",   0,      ARMVFP2, 0},
+	{"vcvt(bfi)",   0,      ARMVFP2, 0},
+	{"vmovbrs",     0,      ARMVFP2, 0},
+	{"vmsr",        0,      ARMVFP2, 0},
+	{"vmovbrc",     0,      ARMVFP2, 0},
+	{"vmrs",        0,      ARMVFP2, 0},
+	{"vmovbcr",     0,      ARMVFP2, 0},
+	{"vmovbrrss",   0,      ARMVFP2, 0},
+	{"vmovbrrd",    0,      ARMVFP2, 0},
+	{"vstr",        0,      ARMVFP2, 0},
+	{"vpush",       0,      ARMVFP2, 0},
+	{"vstm",        0,      ARMVFP2, 0},
+	{"vpop",        0,      ARMVFP2, 0},
+	{"vldr",        0,      ARMVFP2, 0},
+	{"vldm",        0,      ARMVFP2, 0},
+
 	{"srs"	,  0	,  6	,  0},
 	{"rfe"	,  0	,  6	,  0},
 	{"bkpt"	,  0	,  3	,  0},
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 4cd8fe6ac..b4ee64203 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3363,9 +3363,40 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index)    { UN
 typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
 
 const transop_fp_t arm_instruction_trans[] = {
-	#define VFP_INTERPRETER_TABLE
-	#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
-	#undef VFP_INTERPRETER_TABLE
+	INTERPRETER_TRANSLATE(vmla),
+	INTERPRETER_TRANSLATE(vmls),
+	INTERPRETER_TRANSLATE(vnmla),
+	INTERPRETER_TRANSLATE(vnmla),
+	INTERPRETER_TRANSLATE(vnmls),
+	INTERPRETER_TRANSLATE(vnmul),
+	INTERPRETER_TRANSLATE(vmul),
+	INTERPRETER_TRANSLATE(vadd),
+	INTERPRETER_TRANSLATE(vsub),
+	INTERPRETER_TRANSLATE(vdiv),
+	INTERPRETER_TRANSLATE(vmovi),
+	INTERPRETER_TRANSLATE(vmovr),
+	INTERPRETER_TRANSLATE(vabs),
+	INTERPRETER_TRANSLATE(vneg),
+	INTERPRETER_TRANSLATE(vsqrt),
+	INTERPRETER_TRANSLATE(vcmp),
+	INTERPRETER_TRANSLATE(vcmp2),
+	INTERPRETER_TRANSLATE(vcvtbds),
+	INTERPRETER_TRANSLATE(vcvtbff),
+	INTERPRETER_TRANSLATE(vcvtbfi),
+	INTERPRETER_TRANSLATE(vmovbrs),
+	INTERPRETER_TRANSLATE(vmsr),
+	INTERPRETER_TRANSLATE(vmovbrc),
+	INTERPRETER_TRANSLATE(vmrs),
+	INTERPRETER_TRANSLATE(vmovbcr),
+	INTERPRETER_TRANSLATE(vmovbrrss),
+	INTERPRETER_TRANSLATE(vmovbrrd),
+	INTERPRETER_TRANSLATE(vstr),
+	INTERPRETER_TRANSLATE(vpush),
+	INTERPRETER_TRANSLATE(vstm),
+	INTERPRETER_TRANSLATE(vpop),
+	INTERPRETER_TRANSLATE(vldr),
+	INTERPRETER_TRANSLATE(vldm),
+	
 	INTERPRETER_TRANSLATE(srs),
 	INTERPRETER_TRANSLATE(rfe),
 	INTERPRETER_TRANSLATE(bkpt),
@@ -4206,10 +4237,12 @@ unsigned InterpreterMainLoop(ARMul_State* state)
     // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
     // to a clunky switch statement.
 #if defined __GNUC__ || defined __clang__
-    void *InstLabel[] = {
-		#define VFP_INTERPRETER_LABEL
-		#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
-		#undef VFP_INTERPRETER_LABEL
+	void *InstLabel[] = {
+		&&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST,
+		&&VDIV_INST, &&VMOVI_INST, &&VMOVR_INST, &&VABS_INST, &&VNEG_INST, &&VSQRT_INST, &&VCMP_INST, &&VCMP2_INST, &&VCVTBDS_INST,
+		&&VCVTBFF_INST, &&VCVTBFI_INST, &&VMOVBRS_INST, &&VMSR_INST, &&VMOVBRC_INST, &&VMRS_INST, &&VMOVBCR_INST, &&VMOVBRRSS_INST,
+		&&VMOVBRRD_INST, &&VSTR_INST, &&VPUSH_INST, &&VSTM_INST, &&VPOP_INST, &&VLDR_INST, &&VLDM_INST,
+
 		&&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST,
 		&&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST,
 		&&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST,
@@ -4243,7 +4276,7 @@ unsigned InterpreterMainLoop(ARMul_State* state)
 	DISPATCH:
 	{
 		if (!cpu->NirqSig) {
-                	if (!(cpu->Cpsr & 0x80)) {
+			if (!(cpu->Cpsr & 0x80)) {
 				goto END;
 			}
 		}