summaryrefslogtreecommitdiffstats
path: root/src/core/arm/interpreter/armemu.cpp
diff options
context:
space:
mode:
authorLioncash <mathew1800@gmail.com>2014-12-18 17:11:30 +0100
committerLioncash <mathew1800@gmail.com>2014-12-18 17:45:40 +0100
commit4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1 (patch)
treee4bdcac218ed173bfc1995f2d74806e4a286771d /src/core/arm/interpreter/armemu.cpp
parentMerge pull request #299 from lioncash/join (diff)
downloadyuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.tar
yuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.tar.gz
yuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.tar.bz2
yuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.tar.lz
yuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.tar.xz
yuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.tar.zst
yuzu-4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1.zip
Diffstat (limited to '')
-rw-r--r--src/core/arm/interpreter/armemu.cpp33
1 files changed, 29 insertions, 4 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index b9ac8b9ad..f4452f356 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -5839,21 +5839,46 @@ L_stm_s_takeabort:
const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
+ s32 lo_result;
+ s32 hi_result;
+
// SSUB16
if ((instr & 0xFF0) == 0xf70) {
- state->Reg[rd_idx] = ((rn_lo - rm_lo) & 0xFFFF) | (((rn_hi - rm_hi) & 0xFFFF) << 16);
+ lo_result = (rn_lo - rm_lo);
+ hi_result = (rn_hi - rm_hi);
}
// SADD16
else if ((instr & 0xFF0) == 0xf10) {
- state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16);
+ lo_result = (rn_lo + rm_lo);
+ hi_result = (rn_hi + rm_hi);
}
// SSAX
else if ((instr & 0xFF0) == 0xf50) {
- state->Reg[rd_idx] = ((rn_lo + rm_hi) & 0xFFFF) | (((rn_hi - rm_lo) & 0xFFFF) << 16);
+ lo_result = (rn_lo + rm_hi);
+ hi_result = (rn_hi - rm_lo);
}
// SASX
else {
- state->Reg[rd_idx] = ((rn_lo - rm_hi) & 0xFFFF) | (((rn_hi + rm_lo) & 0xFFFF) << 16);
+ lo_result = (rn_lo - rm_hi);
+ hi_result = (rn_hi + rm_lo);
+ }
+
+ state->Reg[rd_idx] = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
+
+ if (lo_result >= 0) {
+ state->Cpsr |= (1 << 16);
+ state->Cpsr |= (1 << 17);
+ } else {
+ state->Cpsr &= ~(1 << 16);
+ state->Cpsr &= ~(1 << 17);
+ }
+
+ if (hi_result >= 0) {
+ state->Cpsr |= (1 << 18);
+ state->Cpsr |= (1 << 19);
+ } else {
+ state->Cpsr &= ~(1 << 18);
+ state->Cpsr &= ~(1 << 19);
}
return 1;
} else {