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| author | Lioncash <mathew1800@gmail.com> | 2014-12-23 04:10:47 +0100 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2014-12-23 05:51:59 +0100 |
| commit | 8e2accd9746d33116c6398e6f30db5b8b4e1f188 (patch) | |
| tree | c39bd43bf51a9eead458b8743e0cc925947edbd4 /src/core/arm/interpreter/armsupp.cpp | |
| parent | Merge pull request #322 from chinhodado/master (diff) | |
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Diffstat (limited to '')
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index 30519f216..b31c0ea24 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp @@ -227,8 +227,9 @@ ARMul_CPSRAltered (ARMul_State * state) //state->Cpsr &= ~CBIT; ASSIGNV ((state->Cpsr & VBIT) != 0); //state->Cpsr &= ~VBIT; - ASSIGNS ((state->Cpsr & SBIT) != 0); - //state->Cpsr &= ~SBIT; + ASSIGNQ ((state->Cpsr & QBIT) != 0); + //state->Cpsr &= ~QBIT; + state->GEFlag = (state->Cpsr & 0x000F0000); #ifdef MODET ASSIGNT ((state->Cpsr & TBIT) != 0); //state->Cpsr &= ~TBIT; |