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authorFernandoS27 <fsahmkow27@gmail.com>2021-03-28 19:47:52 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:25 +0200
commit613b48c4a2ce71a0d0eaba17fe164f4a2e4a3db5 (patch)
treea8d2d2eb8284f1b35184e4ee07e25709ecce0596 /src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
parentshader: Implement TLDS (diff)
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Diffstat (limited to '')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_image.cpp15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
index 310cc7af7..2cd6b38c4 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
@@ -161,6 +161,10 @@ Id EmitBindlessImageQueryDimensions(EmitContext&) {
throw LogicError("Unreachable instruction");
}
+Id EmitBindlessImageQueryLod(EmitContext&) {
+ throw LogicError("Unreachable instruction");
+}
+
Id EmitBoundImageSampleImplicitLod(EmitContext&) {
throw LogicError("Unreachable instruction");
}
@@ -193,6 +197,10 @@ Id EmitBoundImageQueryDimensions(EmitContext&) {
throw LogicError("Unreachable instruction");
}
+Id EmitBoundImageQueryLod(EmitContext&) {
+ throw LogicError("Unreachable instruction");
+}
+
Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
Id bias_lc, Id offset) {
const auto info{inst->Flags<IR::TextureInstInfo>()};
@@ -287,4 +295,11 @@ Id EmitImageQueryDimensions(EmitContext& ctx, IR::Inst* inst, const IR::Value& i
throw LogicError("Unspecified image type {}", info.type.Value());
}
+Id EmitImageQueryLod(EmitContext& ctx, IR::Inst*, const IR::Value& index, Id coords) {
+ const Id zero{ctx.f32_zero_value};
+ const Id image{TextureImage(ctx, index)};
+ return ctx.OpCompositeConstruct(ctx.F32[4], ctx.OpImageQueryLod(ctx.F32[2], image, coords),
+ zero, zero);
+}
+
} // namespace Shader::Backend::SPIRV