4 files changed, 57 insertions, 44 deletions

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.cpp
index 10bb01d99..20458d2ad 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.cpp
@@ -29,6 +29,49 @@ IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32
     }
 }
 
+IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
+                              CompareOp compare_op, bool is_signed) {
+    const IR::U32 zero{ir.Imm32(0)};
+    const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
+    const IR::U1 z_flag{ir.GetZFlag()};
+    const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
+    const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
+                                      : ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
+                                                      ir.ILessThan(operand_2, zero, true))};
+    switch (compare_op) {
+    case CompareOp::False:
+        return ir.Imm1(false);
+    case CompareOp::LessThan:
+        return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
+                                ir.ILessThan(intermediate, zero, true))};
+    case CompareOp::Equal:
+        return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
+    case CompareOp::LessThanEqual: {
+        const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
+                                        ir.ILessThan(intermediate, zero, true))};
+        return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
+    }
+    case CompareOp::GreaterThan: {
+        const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
+                                        ir.IGreaterThan(intermediate, zero, true))};
+        const IR::U1 not_z{ir.LogicalNot(z_flag)};
+        return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
+    }
+    case CompareOp::NotEqual:
+        return ir.LogicalOr(ir.INotEqual(intermediate, zero),
+                            ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
+    case CompareOp::GreaterThanEqual: {
+        const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
+                                        ir.IGreaterThanEqual(intermediate, zero, true))};
+        return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
+    }
+    case CompareOp::True:
+        return ir.Imm1(true);
+    default:
+        throw NotImplementedException("Invalid compare op {}", compare_op);
+    }
+}
+
 IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
                         BooleanOp bop) {
     switch (bop) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h b/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h
index f584060b3..214d0af3c 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h
@@ -11,6 +11,10 @@ namespace Shader::Maxwell {
 [[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
                                     const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
 
+[[nodiscard]] IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
+                                            const IR::U32& operand_2, CompareOp compare_op,
+                                            bool is_signed);
+
 [[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
                                       const IR::U1& predicate_2, BooleanOp bop);
 
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_compare_and_set.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_compare_and_set.cpp
index 34fa7345c..8ce1aee04 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_compare_and_set.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_compare_and_set.cpp
@@ -9,49 +9,6 @@
 
 namespace Shader::Maxwell {
 namespace {
-IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
-                              CompareOp compare_op, bool is_signed) {
-    const IR::U32 zero{ir.Imm32(0)};
-    const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
-    const IR::U1 z_flag{ir.GetZFlag()};
-    const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
-    const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
-                                      : ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
-                                                      ir.ILessThan(operand_2, zero, true))};
-    switch (compare_op) {
-    case CompareOp::False:
-        return ir.Imm1(false);
-    case CompareOp::LessThan:
-        return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
-                                ir.ILessThan(intermediate, zero, true))};
-    case CompareOp::Equal:
-        return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
-    case CompareOp::LessThanEqual: {
-        const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
-                                        ir.ILessThan(intermediate, zero, true))};
-        return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
-    }
-    case CompareOp::GreaterThan: {
-        const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
-                                        ir.IGreaterThan(intermediate, zero, true))};
-        const IR::U1 not_z{ir.LogicalNot(z_flag)};
-        return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
-    }
-    case CompareOp::NotEqual:
-        return ir.LogicalOr(ir.INotEqual(intermediate, zero),
-                            ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
-    case CompareOp::GreaterThanEqual: {
-        const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
-                                        ir.IGreaterThanEqual(intermediate, zero, true))};
-        return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
-    }
-    case CompareOp::True:
-        return ir.Imm1(true);
-    default:
-        throw NotImplementedException("Invalid compare op {}", compare_op);
-    }
-}
-
 IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
                    CompareOp compare_op, bool is_signed, bool x) {
     return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_set_predicate.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_set_predicate.cpp
index 7743701d0..bee10e5b9 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_set_predicate.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_set_predicate.cpp
@@ -9,6 +9,12 @@
 
 namespace Shader::Maxwell {
 namespace {
+IR::U1 IsetpCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
+                    CompareOp compare_op, bool is_signed, bool x) {
+    return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
+             : IntegerCompare(ir, operand_1, operand_2, compare_op, is_signed);
+}
+
 void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
     union {
         u64 raw;
@@ -17,15 +23,18 @@ void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
         BitField<8, 8, IR::Reg> src_reg_a;
         BitField<39, 3, IR::Pred> bop_pred;
         BitField<42, 1, u64> neg_bop_pred;
+        BitField<43, 1, u64> x;
         BitField<45, 2, BooleanOp> bop;
         BitField<48, 1, u64> is_signed;
         BitField<49, 3, CompareOp> compare_op;
     } const isetp{insn};
 
+    const bool is_signed{isetp.is_signed != 0};
+    const bool x{isetp.x != 0};
     const BooleanOp bop{isetp.bop};
     const CompareOp compare_op{isetp.compare_op};
     const IR::U32 op_a{v.X(isetp.src_reg_a)};
-    const IR::U1 comparison{IntegerCompare(v.ir, op_a, op_b, compare_op, isetp.is_signed != 0)};
+    const IR::U1 comparison{IsetpCompare(v.ir, op_a, op_b, compare_op, is_signed, x)};
     const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
     const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
     const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};