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| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-04-09 23:41:41 +0200 |
|---|---|---|
| committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-04-16 02:16:10 +0200 |
| commit | 64613db6052dfe0c056ce3d6ead21ae9a32f03ae (patch) | |
| tree | 9fa4a632c8fc050b6176ebbca727c27757f95662 /src/video_core/shader/shader_ir.h | |
| parent | shader_ir/decode: Reduce severity of unimplemented half-float FTZ (diff) | |
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Diffstat (limited to '')
| -rw-r--r-- | src/video_core/shader/shader_ir.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index 0ae51389b..d329da58d 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h @@ -114,6 +114,7 @@ enum class OperationCode { HFma, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b, f16vec2 c) -> f16vec2 HAbsolute, /// (f16vec2 a) -> f16vec2 HNegate, /// (f16vec2 a, bool first, bool second) -> f16vec2 + HClamp, /// (f16vec2 src, float min, float max) -> f16vec2 HMergeF32, /// (f16vec2 src) -> float HMergeH0, /// (f16vec2 dest, f16vec2 src) -> f16vec2 HMergeH1, /// (f16vec2 dest, f16vec2 src) -> f16vec2 @@ -716,6 +717,8 @@ private: Node HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge); /// Conditionally absolute/negated half float pair. Absolute is applied first Node GetOperandAbsNegHalf(Node value, bool absolute, bool negate); + /// Conditionally saturates a half float pair + Node GetSaturatedHalfFloat(Node value, bool saturate = true); /// Returns a predicate comparing two floats Node GetPredicateComparisonFloat(Tegra::Shader::PredCondition condition, Node op_a, Node op_b); |