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authorReinUsesLisp <reinuseslisp@airmail.cc>2019-05-10 09:17:48 +0200
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-06-21 02:36:12 +0200
commit345e73f2feb0701e3c3099d002a1c21fb524eae4 (patch)
treec8c934dfec804d04a29f8ee27124274f5f999fb8 /src/video_core/texture_cache/surface_base.cpp
parenttexture_cache: Change internal cache from lists to vectors (diff)
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Diffstat (limited to '')
-rw-r--r--src/video_core/texture_cache/surface_base.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/video_core/texture_cache/surface_base.cpp b/src/video_core/texture_cache/surface_base.cpp
index 36ca72b4a..510d1aef5 100644
--- a/src/video_core/texture_cache/surface_base.cpp
+++ b/src/video_core/texture_cache/surface_base.cpp
@@ -22,7 +22,6 @@ SurfaceBaseImpl::SurfaceBaseImpl(GPUVAddr gpu_addr, const SurfaceParams& params)
: params{params}, mipmap_sizes(params.num_levels),
mipmap_offsets(params.num_levels), gpu_addr{gpu_addr}, host_memory_size{
params.GetHostSizeInBytes()} {
-
std::size_t offset = 0;
for (u32 level = 0; level < params.num_levels; ++level) {
const std::size_t mipmap_size{params.GetGuestMipmapSize(level)};
@@ -75,7 +74,7 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
return;
}
if (params.is_tiled) {
- ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture target {}",
+ ASSERT_MSG(params.block_width == 0, "Block width is defined as {} on texture target {}",
params.block_width, static_cast<u32>(params.target));
for (u32 level = 0; level < params.num_levels; ++level) {
const std::size_t host_offset{params.GetHostMipmapLevelOffset(level)};