diff options
| -rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 33 | ||||
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 18 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 17 |
3 files changed, 50 insertions, 18 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 23e70cd8a..ef12d9300 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -156,16 +156,15 @@ void Maxwell3D::ProcessQueryGet() { // TODO(Subv): Support the other query units. ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop, "Units other than CROP are unimplemented"); - ASSERT_MSG(regs.query.query_get.short_query, - "Writing the entire query result structure is unimplemented"); u32 value = Memory::Read32(*address); - u32 result = 0; + u64 result = 0; // TODO(Subv): Support the other query variables switch (regs.query.query_get.select) { case Regs::QuerySelect::Zero: - result = 0; + // This seems to actually write the query sequence to the query address. + result = regs.query.query_sequence; break; default: UNIMPLEMENTED_MSG("Unimplemented query select type {}", @@ -174,15 +173,31 @@ void Maxwell3D::ProcessQueryGet() { // TODO(Subv): Research and implement how query sync conditions work. + struct LongQueryResult { + u64_le value; + u64_le timestamp; + }; + static_assert(sizeof(LongQueryResult) == 16, "LongQueryResult has wrong size"); + switch (regs.query.query_get.mode) { case Regs::QueryMode::Write: case Regs::QueryMode::Write2: { - // Write the current query sequence to the sequence address. u32 sequence = regs.query.query_sequence; - Memory::Write32(*address, sequence); - - // TODO(Subv): Write the proper query response structure to the address when not using short - // mode. + if (regs.query.query_get.short_query) { + // Write the current query sequence to the sequence address. + // TODO(Subv): Find out what happens if you use a long query type but mark it as a short + // query. + Memory::Write32(*address, sequence); + } else { + // Write the 128-bit result structure in long mode. Note: We emulate an infinitely fast + // GPU, this command may actually take a while to complete in real hardware due to GPU + // wait queues. + LongQueryResult query_result{}; + query_result.value = result; + // TODO(Subv): Generate a real GPU timestamp and write it here instead of 0 + query_result.timestamp = 0; + Memory::WriteBlock(*address, &query_result, sizeof(query_result)); + } break; } default: diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index fd4e0746e..da64430e9 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -270,8 +270,22 @@ union Instruction { } tex; union { - // TODO(bunnei): This is just a guess, needs to be verified - BitField<52, 1, u64> enable_g_component; + BitField<50, 3, u64> component_mask_selector; + BitField<28, 8, Register> gpr28; + + bool HasTwoDestinations() const { + return gpr28.Value() != Register::ZeroIndex; + } + + bool IsComponentEnabled(size_t component) const { + static constexpr std::array<size_t, 5> one_dest_mask{0x1, 0x2, 0x4, 0x8, 0x3}; + static constexpr std::array<size_t, 5> two_dest_mask{0x7, 0xb, 0xd, 0xe, 0xf}; + const auto& mask{HasTwoDestinations() ? two_dest_mask : one_dest_mask}; + + ASSERT(component_mask_selector < mask.size()); + + return ((1 << component) & mask[component_mask_selector]) != 0; + } } texs; BitField<61, 1, u64> is_b_imm; diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 86d880dfc..bb5209a7e 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -938,18 +938,21 @@ private: // TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA goes // into gpr28+0 and gpr28+1 size_t offset{}; + for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) { for (unsigned elem = 0; elem < 2; ++elem) { - if (dest + elem >= Register::ZeroIndex) { - // Skip invalid register values - break; + if (!instr.texs.IsComponentEnabled(elem)) { + // Skip disabled components + continue; } regs.SetRegisterToFloat(dest, elem + offset, texture, 1, 4, false, elem); - if (!instr.texs.enable_g_component) { - // Skip the second component - break; - } } + + if (!instr.texs.HasTwoDestinations()) { + // Skip the second destination + break; + } + offset += 2; } --shader.scope; |