diff options
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.cpp | 4 | ||||
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.h | 37 | ||||
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 64 |
3 files changed, 64 insertions, 41 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 9f3b90fd0..12181d0ec 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -413,7 +413,7 @@ int decode_arm_instr(uint32_t instr, int32_t *idx) { if (instr != arm_instruction[i].content[base + 2]) { break; } - } else if (BITS(arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { + } else if (BITS(instr, arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { break; } base += 3; @@ -429,7 +429,7 @@ int decode_arm_instr(uint32_t instr, int32_t *idx) { if (n != 0) { base = 0; while (n) { - if (BITS(arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { + if (BITS(instr, arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { break; } base += 3; diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h index ee8ff5992..4b5f5ad7e 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.h +++ b/src/core/arm/dyncom/arm_dyncom_dec.h @@ -4,43 +4,6 @@ #pragma once -#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) -#define BIT(n) ((instr >> (n)) & 1) - -// For MUL instructions -#define RDHi ((instr >> 16) & 0xF) -#define RDLo ((instr >> 12) & 0xF) -#define MUL_RD ((instr >> 16) & 0xF) -#define MUL_RN ((instr >> 12) & 0xF) -#define RS ((instr >> 8) & 0xF) -#define RD ((instr >> 12) & 0xF) -#define RN ((instr >> 16) & 0xF) -#define RM (instr & 0xF) - -// CP15 registers -#define OPCODE_1 BITS(21, 23) -#define CRn BITS(16, 19) -#define CRm BITS(0, 3) -#define OPCODE_2 BITS(5, 7) - -#define I BIT(25) -#define S BIT(20) - -#define SHIFT BITS(5,6) -#define SHIFT_IMM BITS(7,11) -#define IMMH BITS(8,11) -#define IMML BITS(0,3) - -#define LSPBIT BIT(24) -#define LSUBIT BIT(23) -#define LSBBIT BIT(22) -#define LSWBIT BIT(21) -#define LSLBIT BIT(20) -#define LSSHBITS BITS(5,6) -#define OFFSET12 BITS(0,11) -#define SBIT BIT(20) -#define DESTReg (BITS (12, 15)) - int decode_arm_instr(uint32_t instr, int32_t *idx); enum DECODE_STATUS { diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index cfa6de8fc..2765cb36e 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -2156,7 +2156,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) return INTERPRETER_TRANSLATE(rev)(inst, index); } -static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("RFE"); } +static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = AL; + inst_base->idx = index; + inst_base->br = INDIRECT_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + return inst_base; +} + static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) { arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst)); @@ -2570,7 +2585,23 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) inst_base->load_r15 = 1; return inst_base; } -static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); } + +static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) +{ + arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + inst_base->cond = AL; + inst_base->idx = index; + inst_base->br = NON_BRANCH; + inst_base->load_r15 = 0; + + inst_cream->inst = inst; + inst_cream->get_addr = get_calc_addr_op(inst); + + return inst_base; +} + static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) { arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); @@ -5293,6 +5324,20 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } RFE_INST: + { + // RFE is unconditional + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + u32 address = 0; + inst_cream->get_addr(cpu, inst_cream->inst, address, 1); + + cpu->Cpsr = ReadMemory32(cpu, address); + cpu->Reg[15] = ReadMemory32(cpu, address + 4); + + INC_PC(sizeof(ldst_inst)); + goto DISPATCH; + } + RSB_INST: { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { @@ -5934,6 +5979,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) { } SRS_INST: + { + // SRS is unconditional + ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; + + u32 address = 0; + inst_cream->get_addr(cpu, inst_cream->inst, address, 1); + + WriteMemory32(cpu, address + 0, cpu->Reg[14]); + WriteMemory32(cpu, address + 4, cpu->Spsr_copy); + + cpu->Reg[15] += GET_INST_SIZE(cpu); + INC_PC(sizeof(ldst_inst)); + FETCH_INST; + GOTO_NEXT_INST; + } SSAT_INST: { |