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-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp28
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp607
-rw-r--r--src/core/arm/interpreter/arminit.cpp1
-rw-r--r--src/core/arm/interpreter/armsupp.cpp2
-rw-r--r--src/core/arm/skyeye_common/armmmu.h2
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp128
6 files changed, 454 insertions, 314 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 12181d0ec..3887189f1 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -181,7 +181,11 @@ const ISEITEM arm_instruction[] = {
{ "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 },
{ "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 },
{ "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 },
- { "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 },
+ { "msr", 3, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000001 },
+ { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 19, 0x00000004 },
+ { "msr", 5, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 19, 19, 0x00000001, 16, 17, 0x00000000 },
+ { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 17, 0x00000001 },
+ { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 17, 17, 0x00000001 },
{ "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 },
{ "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 },
{ "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 },
@@ -190,12 +194,17 @@ const ISEITEM arm_instruction[] = {
{ "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 },
{ "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 },
{ "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
- { "swi", 1, 0, 24, 27, 0x0000000f },
- { "bbl", 1, 0, 25, 27, 0x00000005 },
{ "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 },
{ "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 },
{ "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 },
{ "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 },
+ { "nop", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000000 },
+ { "yield", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000001 },
+ { "wfe", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000002 },
+ { "wfi", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000003 },
+ { "sev", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000004 },
+ { "swi", 1, 0, 24, 27, 0x0000000f },
+ { "bbl", 1, 0, 25, 27, 0x00000005 },
};
const ISEITEM arm_exclusion_code[] = {
@@ -375,6 +384,10 @@ const ISEITEM arm_exclusion_code[] = {
{ "mrc", 0, 6, 0 },
{ "mcr", 0, 0, 0 },
{ "msr", 0, 0, 0 },
+ { "msr", 0, 0, 0 },
+ { "msr", 0, 0, 0 },
+ { "msr", 0, 0, 0 },
+ { "msr", 0, 0, 0 },
{ "ldrb", 0, 0, 0 },
{ "strb", 0, 0, 0 },
{ "ldr", 0, 0, 0 },
@@ -383,12 +396,17 @@ const ISEITEM arm_exclusion_code[] = {
{ "cdp", 0, 0, 0 },
{ "stc", 0, 0, 0 },
{ "ldc", 0, 0, 0 },
- { "swi", 0, 0, 0 },
- { "bbl", 0, 0, 0 },
{ "ldrexd", 0, ARMV6K, 0 },
{ "strexd", 0, ARMV6K, 0 },
{ "ldrexh", 0, ARMV6K, 0 },
{ "strexh", 0, ARMV6K, 0 },
+ { "nop", 0, ARMV6K, 0 },
+ { "yield", 0, ARMV6K, 0 },
+ { "wfe", 0, ARMV6K, 0 },
+ { "wfi", 0, ARMV6K, 0 },
+ { "sev", 0, ARMV6K, 0 },
+ { "swi", 0, 0, 0 },
+ { "bbl", 0, 0, 0 },
{ "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
{ "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 315b4cc91..66282a7e6 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -10,9 +10,10 @@
#include "common/logging/log.h"
#include "common/profiler.h"
-#include "core/mem_map.h"
+#include "core/memory.h"
#include "core/hle/svc.h"
#include "core/arm/disassembler/arm_disasm.h"
+#include "core/arm/dyncom/arm_dyncom_dec.h"
#include "core/arm/dyncom/arm_dyncom_interpreter.h"
#include "core/arm/dyncom/arm_dyncom_thumb.h"
#include "core/arm/dyncom/arm_dyncom_run.h"
@@ -68,6 +69,67 @@ static void remove_exclusive(ARMul_State* state, ARMword addr){
state->exclusive_tag = 0xFFFFFFFF;
}
+static int CondPassed(ARMul_State* cpu, unsigned int cond) {
+ const u32 NFLAG = cpu->NFlag;
+ const u32 ZFLAG = cpu->ZFlag;
+ const u32 CFLAG = cpu->CFlag;
+ const u32 VFLAG = cpu->VFlag;
+
+ int temp = 0;
+
+ switch (cond) {
+ case 0x0:
+ temp = ZFLAG;
+ break;
+ case 0x1: // NE
+ temp = !ZFLAG;
+ break;
+ case 0x2: // CS
+ temp = CFLAG;
+ break;
+ case 0x3: // CC
+ temp = !CFLAG;
+ break;
+ case 0x4: // MI
+ temp = NFLAG;
+ break;
+ case 0x5: // PL
+ temp = !NFLAG;
+ break;
+ case 0x6: // VS
+ temp = VFLAG;
+ break;
+ case 0x7: // VC
+ temp = !VFLAG;
+ break;
+ case 0x8: // HI
+ temp = (CFLAG && !ZFLAG);
+ break;
+ case 0x9: // LS
+ temp = (!CFLAG || ZFLAG);
+ break;
+ case 0xa: // GE
+ temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
+ break;
+ case 0xb: // LT
+ temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
+ break;
+ case 0xc: // GT
+ temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
+ break;
+ case 0xd: // LE
+ temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
+ break;
+ case 0xe: // AL
+ temp = 1;
+ break;
+ case 0xf:
+ temp = 1;
+ break;
+ }
+ return temp;
+}
+
static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) {
unsigned int immed_8 = BITS(sht_oper, 0, 7);
unsigned int rotate_imm = BITS(sht_oper, 8, 11);
@@ -224,14 +286,12 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw);
-typedef struct _ldst_inst {
+struct ldst_inst {
unsigned int inst;
get_addr_fp_t get_addr;
-} ldst_inst;
+};
#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0)
-int CondPassed(ARMul_State* cpu, unsigned int cond);
-
#define LnSWoUB(s) glue(LnSWoUB, s)
#define MLnS(s) glue(MLnS, s)
#define LdnStM(s) glue(LdnStM, s)
@@ -647,255 +707,248 @@ static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, u
virt_addr = addr;
}
-typedef struct _arm_inst {
+struct arm_inst {
unsigned int idx;
unsigned int cond;
int br;
int load_r15;
char component[0];
-} arm_inst;
+};
-typedef struct generic_arm_inst {
+struct generic_arm_inst {
u32 Ra;
u32 Rm;
u32 Rn;
u32 Rd;
u8 op1;
u8 op2;
-} generic_arm_inst;
+};
-typedef struct _adc_inst {
+struct adc_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} adc_inst;
+};
-typedef struct _add_inst {
+struct add_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} add_inst;
+};
-typedef struct _orr_inst {
+struct orr_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} orr_inst;
+};
-typedef struct _and_inst {
+struct and_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} and_inst;
+};
-typedef struct _eor_inst {
+struct eor_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} eor_inst;
+};
-typedef struct _bbl_inst {
+struct bbl_inst {
unsigned int L;
int signed_immed_24;
unsigned int next_addr;
unsigned int jmp_addr;
-} bbl_inst;
+};
-typedef struct _bx_inst {
+struct bx_inst {
unsigned int Rm;
-} bx_inst;
+};
-typedef struct _blx_inst {
+struct blx_inst {
union {
int32_t signed_immed_24;
uint32_t Rm;
} val;
unsigned int inst;
-} blx_inst;
+};
-typedef struct _clz_inst {
+struct clz_inst {
unsigned int Rm;
unsigned int Rd;
-} clz_inst;
+};
-typedef struct _cps_inst {
+struct cps_inst {
unsigned int imod0;
unsigned int imod1;
unsigned int mmod;
unsigned int A, I, F;
unsigned int mode;
-} cps_inst;
+};
-typedef struct _clrex_inst {
-} clrex_inst;
+struct clrex_inst {
+};
-typedef struct _cpy_inst {
+struct cpy_inst {
unsigned int Rm;
unsigned int Rd;
-} cpy_inst;
+};
-typedef struct _bic_inst {
+struct bic_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} bic_inst;
+};
-typedef struct _sub_inst {
+struct sub_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} sub_inst;
+};
-typedef struct _tst_inst {
+struct tst_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} tst_inst;
+};
-typedef struct _cmn_inst {
+struct cmn_inst {
unsigned int I;
unsigned int Rn;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} cmn_inst;
+};
-typedef struct _teq_inst {
+struct teq_inst {
unsigned int I;
unsigned int Rn;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} teq_inst;
+};
-typedef struct _stm_inst {
+struct stm_inst {
unsigned int inst;
-} stm_inst;
+};
struct bkpt_inst {
u32 imm;
};
-struct blx1_inst {
- unsigned int addr;
+struct stc_inst {
};
-struct blx2_inst {
- unsigned int Rm;
+struct ldc_inst {
};
-typedef struct _stc_inst {
-} stc_inst;
-
-typedef struct _ldc_inst {
-} ldc_inst;
-
-typedef struct _swi_inst {
+struct swi_inst {
unsigned int num;
-} swi_inst;
+};
-typedef struct _cmp_inst {
+struct cmp_inst {
unsigned int I;
unsigned int Rn;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} cmp_inst;
+};
-typedef struct _mov_inst {
+struct mov_inst {
unsigned int I;
unsigned int S;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} mov_inst;
+};
-typedef struct _mvn_inst {
+struct mvn_inst {
unsigned int I;
unsigned int S;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} mvn_inst;
+};
-typedef struct _rev_inst {
+struct rev_inst {
unsigned int Rd;
unsigned int Rm;
unsigned int op1;
unsigned int op2;
-} rev_inst;
+};
-typedef struct _rsb_inst {
+struct rsb_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} rsb_inst;
+};
-typedef struct _rsc_inst {
+struct rsc_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} rsc_inst;
+};
-typedef struct _sbc_inst {
+struct sbc_inst {
unsigned int I;
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int shifter_operand;
shtop_fp_t shtop_func;
-} sbc_inst;
+};
-typedef struct _mul_inst {
+struct mul_inst {
unsigned int S;
unsigned int Rd;
unsigned int Rs;
unsigned int Rm;
-} mul_inst;
+};
-typedef struct _smul_inst {
+struct smul_inst {
unsigned int Rd;
unsigned int Rs;
unsigned int Rm;
unsigned int x;
unsigned int y;
-} smul_inst;
+};
-typedef struct _umull_inst {
+struct umull_inst {
unsigned int S;
unsigned int RdHi;
unsigned int RdLo;
unsigned int Rs;
unsigned int Rm;
-} umull_inst;
-typedef struct _smlad_inst {
+};
+
+struct smlad_inst {
unsigned int m;
unsigned int Rm;
unsigned int Rd;
@@ -903,58 +956,58 @@ typedef struct _smlad_inst {
unsigned int Rn;
unsigned int op1;
unsigned int op2;
-} smlad_inst;
+};
-typedef struct _smla_inst {
+struct smla_inst {
unsigned int x;
unsigned int y;
unsigned int Rm;
unsigned int Rd;
unsigned int Rs;
unsigned int Rn;
-} smla_inst;
+};
-typedef struct smlalxy_inst {
+struct smlalxy_inst {
unsigned int x;
unsigned int y;
unsigned int RdLo;
unsigned int RdHi;
unsigned int Rm;
unsigned int Rn;
-} smlalxy_inst;
+};
-typedef struct ssat_inst {
+struct ssat_inst {
unsigned int Rn;
unsigned int Rd;
unsigned int imm5;
unsigned int sat_imm;
unsigned int shift_type;
-} ssat_inst;
+};
-typedef struct umaal_inst {
+struct umaal_inst {
unsigned int Rn;
unsigned int Rm;
unsigned int RdHi;
unsigned int RdLo;
-} umaal_inst;
+};
-typedef struct _umlal_inst {
+struct umlal_inst {
unsigned int S;
unsigned int Rm;
unsigned int Rs;
unsigned int RdHi;
unsigned int RdLo;
-} umlal_inst;
+};
-typedef struct _smlal_inst {
+struct smlal_inst {
unsigned int S;
unsigned int Rm;
unsigned int Rs;
unsigned int RdHi;
unsigned int RdLo;
-} smlal_inst;
+};
-typedef struct smlald_inst {
+struct smlald_inst {
unsigned int RdLo;
unsigned int RdHi;
unsigned int Rm;
@@ -962,17 +1015,17 @@ typedef struct smlald_inst {
unsigned int swap;
unsigned int op1;
unsigned int op2;
-} smlald_inst;
+};
-typedef struct _mla_inst {
+struct mla_inst {
unsigned int S;
unsigned int Rn;
unsigned int Rd;
unsigned int Rs;
unsigned int Rm;
-} mla_inst;
+};
-typedef struct _mrc_inst {
+struct mrc_inst {
unsigned int opcode_1;
unsigned int opcode_2;
unsigned int cp_num;
@@ -980,9 +1033,9 @@ typedef struct _mrc_inst {
unsigned int crm;
unsigned int Rd;
unsigned int inst;
-} mrc_inst;
+};
-typedef struct _mcr_inst {
+struct mcr_inst {
unsigned int opcode_1;
unsigned int opcode_2;
unsigned int cp_num;
@@ -990,77 +1043,77 @@ typedef struct _mcr_inst {
unsigned int crm;
unsigned int Rd;
unsigned int inst;
-} mcr_inst;
+};
-typedef struct mcrr_inst {
+struct mcrr_inst {
unsigned int opcode_1;
unsigned int cp_num;
unsigned int crm;
unsigned int rt;
unsigned int rt2;
-} mcrr_inst;
+};
-typedef struct _mrs_inst {
+struct mrs_inst {
unsigned int R;
unsigned int Rd;
-} mrs_inst;
+};
-typedef struct _msr_inst {
+struct msr_inst {
unsigned int field_mask;
unsigned int R;
unsigned int inst;
-} msr_inst;
+};
-typedef struct _pld_inst {
-} pld_inst;
+struct pld_inst {
+};
-typedef struct _sxtb_inst {
+struct sxtb_inst {
unsigned int Rd;
unsigned int Rm;
unsigned int rotate;
-} sxtb_inst;
+};
-typedef struct _sxtab_inst {
+struct sxtab_inst {
unsigned int Rd;
unsigned int Rn;
unsigned int Rm;
unsigned rotate;
-} sxtab_inst;
+};
-typedef struct _sxtah_inst {
+struct sxtah_inst {
unsigned int Rd;
unsigned int Rn;
unsigned int Rm;
unsigned int rotate;
-} sxtah_inst;
+};
-typedef struct _sxth_inst {
+struct sxth_inst {
unsigned int Rd;
unsigned int Rm;
unsigned int rotate;
-} sxth_inst;
+};
-typedef struct _uxtab_inst {
+struct uxtab_inst {
unsigned int Rn;
unsigned int Rd;
unsigned int rotate;
unsigned int Rm;
-} uxtab_inst;
+};
-typedef struct _uxtah_inst {
+struct uxtah_inst {
unsigned int Rn;
unsigned int Rd;
unsigned int rotate;
unsigned int Rm;
-} uxtah_inst;
+};
-typedef struct _uxth_inst {
+struct uxth_inst {
unsigned int Rd;
unsigned int Rm;
unsigned int rotate;
-} uxth_inst;
+};
-typedef struct _cdp_inst {
+struct cdp_inst {
unsigned int opcode_1;
unsigned int CRn;
unsigned int CRd;
@@ -1068,56 +1121,56 @@ typedef struct _cdp_inst {
unsigned int opcode_2;
unsigned int CRm;
unsigned int inst;
-}cdp_inst;
+};
-typedef struct _uxtb_inst {
+struct uxtb_inst {
unsigned int Rd;
unsigned int Rm;
unsigned int rotate;
-} uxtb_inst;
+};
-typedef struct _swp_inst {
+struct swp_inst {
unsigned int Rn;
unsigned int Rd;
unsigned int Rm;
-} swp_inst;
+};
-typedef struct setend_inst {
+struct setend_inst {
unsigned int set_bigend;
-} setend_inst;
+};
-typedef struct _b_2_thumb {
+struct b_2_thumb {
unsigned int imm;
-}b_2_thumb;
-typedef struct _b_cond_thumb {
+};
+struct b_cond_thumb {
unsigned int imm;
unsigned int cond;
-}b_cond_thumb;
+};
-typedef struct _bl_1_thumb {
+struct bl_1_thumb {
unsigned int imm;
-}bl_1_thumb;
-typedef struct _bl_2_thumb {
+};
+struct bl_2_thumb {
unsigned int imm;
-}bl_2_thumb;
-typedef struct _blx_1_thumb {
+};
+struct blx_1_thumb {
unsigned int imm;
unsigned int instr;
-}blx_1_thumb;
+};
-typedef struct _pkh_inst {
+struct pkh_inst {
unsigned int Rm;
unsigned int Rn;
unsigned int Rd;
unsigned char imm;
-} pkh_inst;
+};
typedef arm_inst * ARM_INST_PTR;
#define CACHE_BUFFER_SIZE (64 * 1024 * 2000)
-char inst_buf[CACHE_BUFFER_SIZE];
-int top = 0;
-inline void *AllocBuffer(unsigned int size) {
+static char inst_buf[CACHE_BUFFER_SIZE];
+static int top = 0;
+static inline void *AllocBuffer(unsigned int size) {
int start = top;
top += size;
if (top > CACHE_BUFFER_SIZE) {
@@ -1127,74 +1180,6 @@ inline void *AllocBuffer(unsigned int size) {
return (void *)&inst_buf[start];
}
-int CondPassed(ARMul_State* cpu, unsigned int cond) {
- #define NFLAG cpu->NFlag
- #define ZFLAG cpu->ZFlag
- #define CFLAG cpu->CFlag
- #define VFLAG cpu->VFlag
-
- int temp = 0;
-
- switch (cond) {
- case 0x0:
- temp = ZFLAG;
- break;
- case 0x1: // NE
- temp = !ZFLAG;
- break;
- case 0x6: // VS
- temp = VFLAG;
- break;
- case 0x7: // VC
- temp = !VFLAG;
- break;
- case 0x4: // MI
- temp = NFLAG;
- break;
- case 0x5: // PL
- temp = !NFLAG;
- break;
- case 0x2: // CS
- temp = CFLAG;
- break;
- case 0x3: // CC
- temp = !CFLAG;
- break;
- case 0x8: // HI
- temp = (CFLAG && !ZFLAG);
- break;
- case 0x9: // LS
- temp = (!CFLAG || ZFLAG);
- break;
- case 0xa: // GE
- temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
- break;
- case 0xb: // LT
- temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
- break;
- case 0xc: // GT
- temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
- break;
- case 0xd: // LE
- temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
- break;
- case 0xe: // AL
- temp = 1;
- break;
- case 0xf:
- temp = 1;
- break;
- }
- return temp;
-}
-
-enum DECODE_STATUS {
- DECODE_SUCCESS,
- DECODE_FAILURE
-};
-
-int decode_arm_instr(uint32_t instr, int32_t *idx);
-
static shtop_fp_t get_shtop(unsigned int inst) {
if (BIT(inst, 25)) {
return DPO(Immediate);
@@ -1393,7 +1378,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index)
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
- inst_cream->imm = BITS(inst, 8, 19) | BITS(inst, 0, 3);
+ inst_cream->imm = (BITS(inst, 8, 19) << 4) | BITS(inst, 0, 3);
return inst_base;
}
@@ -2052,6 +2037,19 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
return inst_base;
}
+// NOP introduced in ARMv6K.
+static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ return inst_base;
+}
+
static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index)
{
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst));
@@ -2343,6 +2341,18 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index)
return inst_base;
}
+static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ return inst_base;
+}
+
static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
@@ -3347,6 +3357,40 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index)
return INTERPRETER_TRANSLATE(uxtab16)(inst, index);
}
+static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ return inst_base;
+}
+static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ return inst_base;
+}
+static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index)
+{
+ arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
+
+ inst_base->cond = BITS(inst, 28, 31);
+ inst_base->idx = index;
+ inst_base->br = NON_BRANCH;
+ inst_base->load_r15 = 0;
+
+ return inst_base;
+}
+
// Floating point VFPv3 structures and instructions
#define VFP_INTERPRETER_STRUCT
@@ -3536,6 +3580,10 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(mrc),
INTERPRETER_TRANSLATE(mcr),
INTERPRETER_TRANSLATE(msr),
+ INTERPRETER_TRANSLATE(msr),
+ INTERPRETER_TRANSLATE(msr),
+ INTERPRETER_TRANSLATE(msr),
+ INTERPRETER_TRANSLATE(msr),
INTERPRETER_TRANSLATE(ldrb),
INTERPRETER_TRANSLATE(strb),
INTERPRETER_TRANSLATE(ldr),
@@ -3544,12 +3592,17 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(cdp),
INTERPRETER_TRANSLATE(stc),
INTERPRETER_TRANSLATE(ldc),
- INTERPRETER_TRANSLATE(swi),
- INTERPRETER_TRANSLATE(bbl),
INTERPRETER_TRANSLATE(ldrexd),
INTERPRETER_TRANSLATE(strexd),
INTERPRETER_TRANSLATE(ldrexh),
INTERPRETER_TRANSLATE(strexh),
+ INTERPRETER_TRANSLATE(nop),
+ INTERPRETER_TRANSLATE(yield),
+ INTERPRETER_TRANSLATE(wfe),
+ INTERPRETER_TRANSLATE(wfi),
+ INTERPRETER_TRANSLATE(sev),
+ INTERPRETER_TRANSLATE(swi),
+ INTERPRETER_TRANSLATE(bbl),
// All the thumb instructions should be placed the end of table
INTERPRETER_TRANSLATE(b_2_thumb),
@@ -3723,7 +3776,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
#define FETCH_INST if (inst_base->br != NON_BRANCH) goto DISPATCH; \
inst_base = (arm_inst *)&inst_buf[ptr]
- #define INC_PC(l) ptr += sizeof(arm_inst) + l
+ #define INC_PC(l) ptr += sizeof(arm_inst) + l
+ #define INC_PC_STUB ptr += sizeof(arm_inst)
// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
// clunky switch statement.
@@ -3912,28 +3966,37 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
case 172: goto MRC_INST; \
case 173: goto MCR_INST; \
case 174: goto MSR_INST; \
- case 175: goto LDRB_INST; \
- case 176: goto STRB_INST; \
- case 177: goto LDR_INST; \
- case 178: goto LDRCOND_INST ; \
- case 179: goto STR_INST; \
- case 180: goto CDP_INST; \
- case 181: goto STC_INST; \
- case 182: goto LDC_INST; \
- case 183: goto SWI_INST; \
- case 184: goto BBL_INST; \
- case 185: goto LDREXD_INST; \
- case 186: goto STREXD_INST; \
- case 187: goto LDREXH_INST; \
- case 188: goto STREXH_INST; \
- case 189: goto B_2_THUMB ; \
- case 190: goto B_COND_THUMB ; \
- case 191: goto BL_1_THUMB ; \
- case 192: goto BL_2_THUMB ; \
- case 193: goto BLX_1_THUMB ; \
- case 194: goto DISPATCH; \
- case 195: goto INIT_INST_LENGTH; \
- case 196: goto END; \
+ case 175: goto MSR_INST; \
+ case 176: goto MSR_INST; \
+ case 177: goto MSR_INST; \
+ case 178: goto MSR_INST; \
+ case 179: goto LDRB_INST; \
+ case 180: goto STRB_INST; \
+ case 181: goto LDR_INST; \
+ case 182: goto LDRCOND_INST ; \
+ case 183: goto STR_INST; \
+ case 184: goto CDP_INST; \
+ case 185: goto STC_INST; \
+ case 186: goto LDC_INST; \
+ case 187: goto LDREXD_INST; \
+ case 188: goto STREXD_INST; \
+ case 189: goto LDREXH_INST; \
+ case 190: goto STREXH_INST; \
+ case 191: goto NOP_INST; \
+ case 192: goto YIELD_INST; \
+ case 193: goto WFE_INST; \
+ case 194: goto WFI_INST; \
+ case 195: goto SEV_INST; \
+ case 196: goto SWI_INST; \
+ case 197: goto BBL_INST; \
+ case 198: goto B_2_THUMB ; \
+ case 199: goto B_COND_THUMB ; \
+ case 200: goto BL_1_THUMB ; \
+ case 201: goto BL_2_THUMB ; \
+ case 202: goto BLX_1_THUMB ; \
+ case 203: goto DISPATCH; \
+ case 204: goto INIT_INST_LENGTH; \
+ case 205: goto END; \
}
#endif
@@ -3979,9 +4042,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
&&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST,
&&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
&&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
- &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST,
- &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST,
- &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
+ &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,
+ &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST,
+ &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST,
+ &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&NOP_INST, &&YIELD_INST, &&WFE_INST, &&WFI_INST, &&SEV_INST, &&SWI_INST,&&BBL_INST,
+ &&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
&&INIT_INST_LENGTH,&&END
};
#endif
@@ -5034,6 +5099,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
GOTO_NEXT_INST;
}
+ NOP_INST:
+ {
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC_STUB;
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
PKHBT_INST:
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
@@ -5517,6 +5590,19 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
GOTO_NEXT_INST;
}
+ SEV_INST:
+ {
+ // Stubbed, as SEV is a hint instruction.
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ LOG_TRACE(Core_ARM11, "SEV executed.");
+ }
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC_STUB;
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
SHADD8_INST:
SHADD16_INST:
SHADDSUBX_INST:
@@ -6980,6 +7066,45 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
GOTO_NEXT_INST;
}
+ WFE_INST:
+ {
+ // Stubbed, as WFE is a hint instruction.
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ LOG_TRACE(Core_ARM11, "WFE executed.");
+ }
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC_STUB;
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
+ WFI_INST:
+ {
+ // Stubbed, as WFI is a hint instruction.
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ LOG_TRACE(Core_ARM11, "WFI executed.");
+ }
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC_STUB;
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
+ YIELD_INST:
+ {
+ // Stubbed, as YIELD is a hint instruction.
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ LOG_TRACE(Core_ARM11, "YIELD executed.");
+ }
+
+ cpu->Reg[15] += GET_INST_SIZE(cpu);
+ INC_PC_STUB;
+ FETCH_INST;
+ GOTO_NEXT_INST;
+ }
+
#define VFP_INTERPRETER_IMPL
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
#undef VFP_INTERPRETER_IMPL
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 31b2bab06..680a94a39 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -16,7 +16,6 @@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <cstring>
-#include "core/mem_map.h"
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/armemu.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index 15c6f595b..1b078dc71 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -454,8 +454,6 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
}
else if (crn == 7 && opcode_1 == 0)
{
- LOG_WARNING(Core_ARM11, "Cache operations are not fully implemented.");
-
if (crm == 0 && opcode_2 == 4)
{
cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value;
diff --git a/src/core/arm/skyeye_common/armmmu.h b/src/core/arm/skyeye_common/armmmu.h
index 0463d83c8..c67d7209b 100644
--- a/src/core/arm/skyeye_common/armmmu.h
+++ b/src/core/arm/skyeye_common/armmmu.h
@@ -22,7 +22,7 @@
#include "common/swap.h"
-#include "core/mem_map.h"
+#include "core/memory.h"
#include "core/arm/skyeye_common/armdefs.h"
// Register numbers in the MMU
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 72afe2164..a04bf915c 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -13,10 +13,10 @@
/* VMLA */
/* cond 1110 0D00 Vn-- Vd-- 101X N0M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmla_inst {
+struct vmla_inst {
unsigned int instr;
unsigned int dp_operation;
-} vmla_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index)
@@ -63,10 +63,10 @@ VMLA_INST:
/* VNMLS */
/* cond 1110 0D00 Vn-- Vd-- 101X N1M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmls_inst {
+struct vmls_inst {
unsigned int instr;
unsigned int dp_operation;
-} vmls_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index)
@@ -113,10 +113,10 @@ VMLS_INST:
/* VNMLA */
/* cond 1110 0D01 Vn-- Vd-- 101X N1M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vnmla_inst {
+struct vnmla_inst {
unsigned int instr;
unsigned int dp_operation;
-} vnmla_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index)
@@ -164,10 +164,10 @@ VNMLA_INST:
/* cond 1110 0D01 Vn-- Vd-- 101X N0M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vnmls_inst {
+struct vnmls_inst {
unsigned int instr;
unsigned int dp_operation;
-} vnmls_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index)
@@ -214,10 +214,10 @@ VNMLS_INST:
/* VNMUL */
/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vnmul_inst {
+struct vnmul_inst {
unsigned int instr;
unsigned int dp_operation;
-} vnmul_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index)
@@ -264,10 +264,10 @@ VNMUL_INST:
/* VMUL */
/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmul_inst {
+struct vmul_inst {
unsigned int instr;
unsigned int dp_operation;
-} vmul_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index)
@@ -314,10 +314,10 @@ VMUL_INST:
/* VADD */
/* cond 1110 0D11 Vn-- Vd-- 101X N0M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vadd_inst {
+struct vadd_inst {
unsigned int instr;
unsigned int dp_operation;
-} vadd_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index)
@@ -364,10 +364,10 @@ VADD_INST:
/* VSUB */
/* cond 1110 0D11 Vn-- Vd-- 101X N1M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vsub_inst {
+struct vsub_inst {
unsigned int instr;
unsigned int dp_operation;
-} vsub_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index)
@@ -414,10 +414,10 @@ VSUB_INST:
/* VDIV */
/* cond 1110 1D00 Vn-- Vd-- 101X N0M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vdiv_inst {
+struct vdiv_inst {
unsigned int instr;
unsigned int dp_operation;
-} vdiv_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index)
@@ -465,11 +465,11 @@ VDIV_INST:
/* cond 1110 1D11 im4H Vd-- 101X 0000 im4L */
/* cond 1110 opc1 CRn- CRd- copr op20 CRm- CDP */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovi_inst {
+struct vmovi_inst {
unsigned int single;
unsigned int d;
unsigned int imm;
-} vmovi_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index)
@@ -514,11 +514,11 @@ VMOVI_INST:
/* cond 1110 1D11 0000 Vd-- 101X 01M0 Vm-- */
/* cond 1110 opc1 CRn- CRd- copr op20 CRm- CDP */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovr_inst {
+struct vmovr_inst {
unsigned int single;
unsigned int d;
unsigned int m;
-} vmovr_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index)
@@ -609,10 +609,10 @@ VABS_INST:
/* cond 1110 1D11 0001 Vd-- 101X 11M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vneg_inst {
+struct vneg_inst {
unsigned int instr;
unsigned int dp_operation;
-} vneg_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vneg)(unsigned int inst, int index)
@@ -659,10 +659,10 @@ VNEG_INST:
/* VSQRT */
/* cond 1110 1D11 0001 Vd-- 101X 11M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vsqrt_inst {
+struct vsqrt_inst {
unsigned int instr;
unsigned int dp_operation;
-} vsqrt_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index)
@@ -709,10 +709,10 @@ VSQRT_INST:
/* VCMP VCMPE */
/* cond 1110 1D11 0100 Vd-- 101X E1M0 Vm-- Encoding 1 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vcmp_inst {
+struct vcmp_inst {
unsigned int instr;
unsigned int dp_operation;
-} vcmp_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index)
@@ -759,10 +759,10 @@ VCMP_INST:
/* VCMP VCMPE */
/* cond 1110 1D11 0100 Vd-- 101X E1M0 Vm-- Encoding 2 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vcmp2_inst {
+struct vcmp2_inst {
unsigned int instr;
unsigned int dp_operation;
-} vcmp2_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index)
@@ -809,10 +809,10 @@ VCMP2_INST:
/* VCVTBDS between double and single */
/* cond 1110 1D11 0111 Vd-- 101X 11M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vcvtbds_inst {
+struct vcvtbds_inst {
unsigned int instr;
unsigned int dp_operation;
-} vcvtbds_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index)
@@ -859,10 +859,10 @@ VCVTBDS_INST:
/* VCVTBFF between floating point and fixed point */
/* cond 1110 1D11 1op2 Vd-- 101X X1M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vcvtbff_inst {
+struct vcvtbff_inst {
unsigned int instr;
unsigned int dp_operation;
-} vcvtbff_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index)
@@ -911,10 +911,10 @@ VCVTBFF_INST:
/* VCVTBFI between floating point and integer */
/* cond 1110 1D11 1op2 Vd-- 101X X1M0 Vm-- */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vcvtbfi_inst {
+struct vcvtbfi_inst {
unsigned int instr;
unsigned int dp_operation;
-} vcvtbfi_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
@@ -967,11 +967,11 @@ VCVTBFI_INST:
/* cond 1110 000o Vn-- Rt-- 1010 N001 0000 */
/* cond 1110 op11 CRn- Rt-- copr op21 CRm- MRC */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovbrs_inst {
+struct vmovbrs_inst {
unsigned int to_arm;
unsigned int t;
unsigned int n;
-} vmovbrs_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index)
@@ -1013,10 +1013,10 @@ VMOVBRS_INST:
/* cond 1110 1110 reg- Rt-- 1010 0001 0000 */
/* cond 1110 op10 CRn- Rt-- copr op21 CRm- MCR */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmsr_inst {
+struct vmsr_inst {
unsigned int reg;
unsigned int Rd;
-} vmsr_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
@@ -1040,7 +1040,7 @@ VMSR_INST:
{
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled ,
- and in privilegied mode */
+ and in privileged mode */
/* Exceptions must be checked, according to v7 ref manual */
CHECK_VFP_ENABLED;
@@ -1060,12 +1060,12 @@ VMSR_INST:
/* cond 1110 0XX0 Vd-- Rt-- 1011 DXX1 0000 */
/* cond 1110 op10 CRn- Rt-- copr op21 CRm- MCR */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovbrc_inst {
+struct vmovbrc_inst {
unsigned int esize;
unsigned int index;
unsigned int d;
unsigned int t;
-} vmovbrc_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index)
@@ -1109,10 +1109,10 @@ VMOVBRC_INST:
/* cond 1110 1111 CRn- Rt-- 1010 0001 0000 */
/* cond 1110 op11 CRn- Rt-- copr op21 CRm- MRC */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmrs_inst {
+struct vmrs_inst {
unsigned int reg;
unsigned int Rt;
-} vmrs_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
@@ -1136,7 +1136,7 @@ VMRS_INST:
{
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled,
- and in privilegied mode */
+ and in privileged mode */
/* Exceptions must be checked, according to v7 ref manual */
CHECK_VFP_ENABLED;
@@ -1191,12 +1191,12 @@ VMRS_INST:
/* cond 1110 XXX1 Vd-- Rt-- 1011 NXX1 0000 */
/* cond 1110 op11 CRn- Rt-- copr op21 CRm- MCR */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovbcr_inst {
+struct vmovbcr_inst {
unsigned int esize;
unsigned int index;
unsigned int d;
unsigned int t;
-} vmovbcr_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index)
@@ -1245,12 +1245,12 @@ VMOVBCR_INST:
/* cond 1100 010X Rt2- Rt-- 1010 00X1 Vm-- */
/* cond 1100 0101 Rt2- Rt-- copr opc1 CRm- MRRC */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovbrrss_inst {
+struct vmovbrrss_inst {
unsigned int to_arm;
unsigned int t;
unsigned int t2;
unsigned int m;
-} vmovbrrss_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index)
@@ -1294,12 +1294,12 @@ VMOVBRRSS_INST:
/* cond 1100 010X Rt2- Rt-- 1011 00X1 Vm-- */
/* cond 1100 0101 Rt2- Rt-- copr opc1 CRm- MRRC */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vmovbrrd_inst {
+struct vmovbrrd_inst {
unsigned int to_arm;
unsigned int t;
unsigned int t2;
unsigned int m;
-} vmovbrrd_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index)
@@ -1347,13 +1347,13 @@ VMOVBRRD_INST:
/* VSTR */
/* cond 1101 UD00 Rn-- Vd-- 101X imm8 imm8 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vstr_inst {
+struct vstr_inst {
unsigned int single;
unsigned int n;
unsigned int d;
unsigned int imm32;
unsigned int add;
-} vstr_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index)
@@ -1415,12 +1415,12 @@ VSTR_INST:
/* VPUSH */
/* cond 1101 0D10 1101 Vd-- 101X imm8 imm8 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vpush_inst {
+struct vpush_inst {
unsigned int single;
unsigned int d;
unsigned int imm32;
unsigned int regs;
-} vpush_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index)
@@ -1488,7 +1488,7 @@ VPUSH_INST:
/* VSTM */
/* cond 110P UDW0 Rn-- Vd-- 101X imm8 imm8 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vstm_inst {
+struct vstm_inst {
unsigned int single;
unsigned int add;
unsigned int wback;
@@ -1496,7 +1496,7 @@ typedef struct _vstm_inst {
unsigned int n;
unsigned int imm32;
unsigned int regs;
-} vstm_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index)
@@ -1570,12 +1570,12 @@ VSTM_INST: /* encoding 1 */
/* VPOP */
/* cond 1100 1D11 1101 Vd-- 101X imm8 imm8 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vpop_inst {
+struct vpop_inst {
unsigned int single;
unsigned int d;
unsigned int imm32;
unsigned int regs;
-} vpop_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index)
@@ -1643,13 +1643,13 @@ VPOP_INST:
/* VLDR */
/* cond 1101 UD01 Rn-- Vd-- 101X imm8 imm8 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vldr_inst {
+struct vldr_inst {
unsigned int single;
unsigned int n;
unsigned int d;
unsigned int imm32;
unsigned int add;
-} vldr_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index)
@@ -1711,7 +1711,7 @@ VLDR_INST:
/* VLDM */
/* cond 110P UDW1 Rn-- Vd-- 101X imm8 imm8 */
#ifdef VFP_INTERPRETER_STRUCT
-typedef struct _vldm_inst {
+struct vldm_inst {
unsigned int single;
unsigned int add;
unsigned int wback;
@@ -1719,7 +1719,7 @@ typedef struct _vldm_inst {
unsigned int n;
unsigned int imm32;
unsigned int regs;
-} vldm_inst;
+};
#endif
#ifdef VFP_INTERPRETER_TRANS
static ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 21:36:11 +0100