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-rw-r--r--src/core/hw/gpu.h84
1 files changed, 44 insertions, 40 deletions
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index da4c345b4..077b6255f 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -17,7 +17,8 @@ namespace GPU {
// Returns index corresponding to the Regs member labeled by field_name
// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
// when used with array elements (e.g. GPU_REG_INDEX(memory_fill_config[0])).
-// For details cf. https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
+// For details cf.
+// https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
// Hopefully, this will be fixed sometime in the future.
// For lack of better alternatives, we currently hardcode the offsets when constant
// expressions are needed via GPU_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
@@ -30,8 +31,9 @@ namespace GPU {
// really is this annoying. This macro just forwards its first argument to GPU_REG_INDEX
// and then performs a (no-op) cast to size_t iff the second argument matches the expected
// field offset. Otherwise, the compiler will fail to compile this code.
-#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
- ((typename std::enable_if<backup_workaround_index == GPU_REG_INDEX(field_name), size_t>::type)GPU_REG_INDEX(field_name))
+#define GPU_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
+ ((typename std::enable_if<backup_workaround_index == GPU_REG_INDEX(field_name), size_t>::type) \
+ GPU_REG_INDEX(field_name))
#endif
// MMIO region 0x1EFxxxxx
@@ -44,18 +46,18 @@ struct Regs {
// support for that.
#define ASSERT_MEMBER_SIZE(name, size_in_bytes)
#else
-#define ASSERT_MEMBER_SIZE(name, size_in_bytes) \
- static_assert(sizeof(name) == size_in_bytes, \
+#define ASSERT_MEMBER_SIZE(name, size_in_bytes) \
+ static_assert(sizeof(name) == size_in_bytes, \
"Structure size and register block length don't match")
#endif
// Components are laid out in reverse byte order, most significant bits first.
enum class PixelFormat : u32 {
- RGBA8 = 0,
- RGB8 = 1,
+ RGBA8 = 0,
+ RGB8 = 1,
RGB565 = 2,
RGB5A1 = 3,
- RGBA4 = 4,
+ RGBA4 = 4,
};
/**
@@ -88,8 +90,8 @@ struct Regs {
BitField<0, 16, u32> value_16bit;
// TODO: Verify component order
- BitField< 0, 8, u32> value_24bit_r;
- BitField< 8, 8, u32> value_24bit_g;
+ BitField<0, 8, u32> value_24bit_r;
+ BitField<8, 8, u32> value_24bit_g;
BitField<16, 8, u32> value_24bit_b;
};
@@ -126,7 +128,7 @@ struct Regs {
union {
u32 size;
- BitField< 0, 16, u32> width;
+ BitField<0, 16, u32> width;
BitField<16, 16, u32> height;
};
@@ -138,7 +140,7 @@ struct Regs {
union {
u32 format;
- BitField< 0, 3, PixelFormat> color_format;
+ BitField<0, 3, PixelFormat> color_format;
};
INSERT_PADDING_WORDS(0x1);
@@ -180,35 +182,37 @@ struct Regs {
union {
u32 output_size;
- BitField< 0, 16, u32> output_width;
+ BitField<0, 16, u32> output_width;
BitField<16, 16, u32> output_height;
};
union {
u32 input_size;
- BitField< 0, 16, u32> input_width;
+ BitField<0, 16, u32> input_width;
BitField<16, 16, u32> input_height;
};
enum ScalingMode : u32 {
- NoScale = 0, // Doesn't scale the image
- ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
- ScaleXY = 2, // Downscales the image in half in both the X and Y axes and applies a box filter
+ NoScale = 0, // Doesn't scale the image
+ ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
+ ScaleXY =
+ 2, // Downscales the image in half in both the X and Y axes and applies a box filter
};
union {
u32 flags;
- BitField< 0, 1, u32> flip_vertically; // flips input data vertically
- BitField< 1, 1, u32> input_linear; // Converts from linear to tiled format
- BitField< 2, 1, u32> crop_input_lines;
- BitField< 3, 1, u32> is_texture_copy; // Copies the data without performing any processing and respecting texture copy fields
- BitField< 5, 1, u32> dont_swizzle;
- BitField< 8, 3, PixelFormat> input_format;
+ BitField<0, 1, u32> flip_vertically; // flips input data vertically
+ BitField<1, 1, u32> input_linear; // Converts from linear to tiled format
+ BitField<2, 1, u32> crop_input_lines;
+ BitField<3, 1, u32> is_texture_copy; // Copies the data without performing any
+ // processing and respecting texture copy fields
+ BitField<5, 1, u32> dont_swizzle;
+ BitField<8, 3, PixelFormat> input_format;
BitField<12, 3, PixelFormat> output_format;
/// Uses some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
- BitField<16, 1, u32> block_32; // TODO(yuriks): unimplemented
+ BitField<16, 1, u32> block_32; // TODO(yuriks): unimplemented
BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
};
@@ -225,14 +229,14 @@ struct Regs {
union {
u32 input_size;
- BitField< 0, 16, u32> input_width;
+ BitField<0, 16, u32> input_width;
BitField<16, 16, u32> input_gap;
};
union {
u32 output_size;
- BitField< 0, 16, u32> output_width;
+ BitField<0, 16, u32> output_width;
BitField<16, 16, u32> output_gap;
};
} texture_copy;
@@ -267,12 +271,12 @@ struct Regs {
return sizeof(Regs) / sizeof(u32);
}
- const u32& operator [] (int index) const {
+ const u32& operator[](int index) const {
const u32* content = reinterpret_cast<const u32*>(this);
return content[index];
}
- u32& operator [] (int index) {
+ u32& operator[](int index) {
u32* content = reinterpret_cast<u32*>(this);
return content[index];
}
@@ -294,28 +298,29 @@ static_assert(std::is_standard_layout<Regs>::value, "Structure does not use stan
// is technically allowed since C++11. This macro should be enabled once MSVC adds
// support for that.
#ifndef _MSC_VER
-#define ASSERT_REG_POSITION(field_name, position) \
- static_assert(offsetof(Regs, field_name) == position * 4, \
- "Field "#field_name" has invalid position")
-
-ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
-ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
-ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
-ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
-ASSERT_REG_POSITION(display_transfer_config, 0x00300);
+#define ASSERT_REG_POSITION(field_name, position) \
+ static_assert(offsetof(Regs, field_name) == position * 4, \
+ "Field " #field_name " has invalid position")
+
+ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
+ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
+ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
+ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
+ASSERT_REG_POSITION(display_transfer_config, 0x00300);
ASSERT_REG_POSITION(command_processor_config, 0x00638);
#undef ASSERT_REG_POSITION
#endif // !defined(_MSC_VER)
-// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value anyway.
+// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value
+// anyway.
static_assert(sizeof(Regs) == 0x1000 * sizeof(u32), "Invalid total size of register set");
extern Regs g_regs;
extern bool g_skip_frame;
template <typename T>
-void Read(T &var, const u32 addr);
+void Read(T& var, const u32 addr);
template <typename T>
void Write(u32 addr, const T data);
@@ -326,5 +331,4 @@ void Init();
/// Shutdown hardware
void Shutdown();
-
} // namespace
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 03:06:29 +0200