1 files changed, 31 insertions, 10 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
index c2ca0873b..18561bc9c 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
@@ -17,9 +17,6 @@ void FFMA(TranslatorVisitor& v, u64 insn, const IR::F32& src_b, const IR::F32& s
         BitField<8, 8, IR::Reg> src_a;
     } const ffma{insn};
 
-    if (sat) {
-        throw NotImplementedException("FFMA SAT");
-    }
     if (cc) {
         throw NotImplementedException("FFMA CC");
     }
@@ -31,7 +28,20 @@ void FFMA(TranslatorVisitor& v, u64 insn, const IR::F32& src_b, const IR::F32& s
         .rounding{CastFpRounding(fp_rounding)},
         .fmz_mode{CastFmzMode(fmz_mode)},
     };
-    v.F(ffma.dest_reg, v.ir.FPFma(op_a, op_b, op_c, fp_control));
+    IR::F32 value{v.ir.FPFma(op_a, op_b, op_c, fp_control)};
+    if (fmz_mode == FmzMode::FMZ && !sat) {
+        // Do not implement FMZ if SAT is enabled, as it does the logic for us.
+        // On D3D9 mode, anything * 0 is zero, even NAN and infinity
+        const IR::F32 zero{v.ir.Imm32(0.0f)};
+        const IR::U1 zero_a{v.ir.FPEqual(op_a, zero)};
+        const IR::U1 zero_b{v.ir.FPEqual(op_b, zero)};
+        const IR::U1 any_zero{v.ir.LogicalOr(zero_a, zero_b)};
+        value = IR::F32{v.ir.Select(any_zero, op_c, value)};
+    }
+    if (sat) {
+        value = v.ir.FPSaturate(value);
+    }
+    v.F(ffma.dest_reg, value);
 }
 
 void FFMA(TranslatorVisitor& v, u64 insn, const IR::F32& src_b, const IR::F32& src_c) {
@@ -54,20 +64,31 @@ void TranslatorVisitor::FFMA_reg(u64 insn) {
     FFMA(*this, insn, GetFloatReg20(insn), GetFloatReg39(insn));
 }
 
-void TranslatorVisitor::FFMA_rc(u64) {
-    throw NotImplementedException("FFMA (rc)");
+void TranslatorVisitor::FFMA_rc(u64 insn) {
+    FFMA(*this, insn, GetFloatReg39(insn), GetFloatCbuf(insn));
 }
 
 void TranslatorVisitor::FFMA_cr(u64 insn) {
     FFMA(*this, insn, GetFloatCbuf(insn), GetFloatReg39(insn));
 }
 
-void TranslatorVisitor::FFMA_imm(u64) {
-    throw NotImplementedException("FFMA (imm)");
+void TranslatorVisitor::FFMA_imm(u64 insn) {
+    FFMA(*this, insn, GetFloatImm20(insn), GetFloatReg39(insn));
 }
 
-void TranslatorVisitor::FFMA32I(u64) {
-    throw NotImplementedException("FFMA32I");
+void TranslatorVisitor::FFMA32I(u64 insn) {
+    union {
+        u64 raw;
+        BitField<0, 8, IR::Reg> src_c; // FFMA32I mirrors the destination and addition register
+        BitField<52, 1, u64> cc;
+        BitField<53, 2, FmzMode> fmz_mode;
+        BitField<55, 1, u64> sat;
+        BitField<56, 1, u64> neg_a;
+        BitField<57, 1, u64> neg_c;
+    } const ffma32i{insn};
+
+    FFMA(*this, insn, GetFloatImm32(insn), F(ffma32i.src_c), ffma32i.neg_a != 0, false,
+         ffma32i.neg_c != 0, ffma32i.sat != 0, ffma32i.cc != 0, ffma32i.fmz_mode, FpRounding::RN);
 }
 
 } // namespace Shader::Maxwell