diff options
Diffstat (limited to 'src/video_core/engines/maxwell_3d.h')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 57 |
1 files changed, 41 insertions, 16 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 92bfda053..b81b0723d 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -34,17 +34,17 @@ public: /// Register structure of the Maxwell3D engine. /// TODO(Subv): This structure will need to be made bigger as more registers are discovered. struct Regs { - static constexpr size_t NUM_REGS = 0xE00; - - static constexpr size_t NumRenderTargets = 8; - static constexpr size_t NumViewports = 16; - static constexpr size_t NumCBData = 16; - static constexpr size_t NumVertexArrays = 32; - static constexpr size_t NumVertexAttributes = 32; - static constexpr size_t MaxShaderProgram = 6; - static constexpr size_t MaxShaderStage = 5; + static constexpr std::size_t NUM_REGS = 0xE00; + + static constexpr std::size_t NumRenderTargets = 8; + static constexpr std::size_t NumViewports = 16; + static constexpr std::size_t NumCBData = 16; + static constexpr std::size_t NumVertexArrays = 32; + static constexpr std::size_t NumVertexAttributes = 32; + static constexpr std::size_t MaxShaderProgram = 6; + static constexpr std::size_t MaxShaderStage = 5; // Maximum number of const buffers per shader stage. - static constexpr size_t MaxConstBuffers = 18; + static constexpr std::size_t MaxConstBuffers = 18; enum class QueryMode : u32 { Write = 0, @@ -127,6 +127,7 @@ public: BitField<21, 6, Size> size; BitField<27, 3, Type> type; BitField<31, 1, u32> bgra; + u32 hex; }; u32 ComponentCount() const { @@ -262,6 +263,10 @@ public: bool IsValid() const { return size != Size::Invalid; } + + bool operator<(const VertexAttribute& other) const { + return hex < other.hex; + } }; enum class PrimitiveTopology : u32 { @@ -438,9 +443,9 @@ public: } }; - bool IsShaderConfigEnabled(size_t index) const { + bool IsShaderConfigEnabled(std::size_t index) const { // The VertexB is always enabled. - if (index == static_cast<size_t>(Regs::ShaderProgram::VertexB)) { + if (index == static_cast<std::size_t>(Regs::ShaderProgram::VertexB)) { return true; } return shader_config[index].enable != 0; @@ -528,7 +533,11 @@ public: u32 stencil_back_mask; u32 stencil_back_func_mask; - INSERT_PADDING_WORDS(0x20); + INSERT_PADDING_WORDS(0x13); + + u32 rt_separate_frag_data; + + INSERT_PADDING_WORDS(0xC); struct { u32 address_high; @@ -545,14 +554,29 @@ public: INSERT_PADDING_WORDS(0x5B); - VertexAttribute vertex_attrib_format[NumVertexAttributes]; + std::array<VertexAttribute, NumVertexAttributes> vertex_attrib_format; INSERT_PADDING_WORDS(0xF); struct { union { BitField<0, 4, u32> count; + BitField<4, 3, u32> map_0; + BitField<7, 3, u32> map_1; + BitField<10, 3, u32> map_2; + BitField<13, 3, u32> map_3; + BitField<16, 3, u32> map_4; + BitField<19, 3, u32> map_5; + BitField<22, 3, u32> map_6; + BitField<25, 3, u32> map_7; }; + + u32 GetMap(std::size_t index) const { + const std::array<u32, NumRenderTargets> maps{map_0, map_1, map_2, map_3, + map_4, map_5, map_6, map_7}; + ASSERT(index < maps.size()); + return maps[index]; + } } rt_control; INSERT_PADDING_WORDS(0x2); @@ -901,7 +925,7 @@ public: std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const; /// Returns the texture information for a specific texture in a specific shader stage. - Texture::FullTextureInfo GetStageTexture(Regs::ShaderStage stage, size_t offset) const; + Texture::FullTextureInfo GetStageTexture(Regs::ShaderStage stage, std::size_t offset) const; private: VideoCore::RasterizerInterface& rasterizer; @@ -963,8 +987,9 @@ ASSERT_REG_POSITION(clear_stencil, 0x368); ASSERT_REG_POSITION(stencil_back_func_ref, 0x3D5); ASSERT_REG_POSITION(stencil_back_mask, 0x3D6); ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D7); +ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB); ASSERT_REG_POSITION(zeta, 0x3F8); -ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458); +ASSERT_REG_POSITION(vertex_attrib_format, 0x458); ASSERT_REG_POSITION(rt_control, 0x487); ASSERT_REG_POSITION(zeta_width, 0x48a); ASSERT_REG_POSITION(zeta_height, 0x48b); |