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-rw-r--r--src/video_core/engines/fermi_2d.cpp4
-rw-r--r--src/video_core/engines/fermi_2d.h10
-rw-r--r--src/video_core/engines/maxwell_3d.cpp4
-rw-r--r--src/video_core/engines/maxwell_3d.h10
-rw-r--r--src/video_core/engines/maxwell_compute.cpp4
-rw-r--r--src/video_core/engines/maxwell_compute.h10
6 files changed, 24 insertions, 18 deletions
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 3d62c321f..7aab163dc 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -6,10 +6,8 @@
namespace Tegra {
namespace Engines {
-namespace Fermi2D {
-void WriteReg(u32 method, u32 value) {}
+void Fermi2D::WriteReg(u32 method, u32 value) {}
-} // namespace Fermi2D
} // namespace Engines
} // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 6f3f5dfbc..8967ddede 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -8,11 +8,15 @@
namespace Tegra {
namespace Engines {
-namespace Fermi2D {
-void WriteReg(u32 method, u32 value);
+class Fermi2D final {
+public:
+ Fermi2D() = default;
+ ~Fermi2D() = default;
-} // namespace Fermi2D
+ /// Write the value to the register identified by method.
+ void WriteReg(u32 method, u32 value);
+};
} // namespace Engines
} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index c2697c960..ccdb310f0 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -6,10 +6,8 @@
namespace Tegra {
namespace Engines {
-namespace Maxwell3D {
-void WriteReg(u32 method, u32 value) {}
+void Maxwell3D::WriteReg(u32 method, u32 value) {}
-} // namespace Maxwell3D
} // namespace Engines
} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 6957fb721..0f4ae1328 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -8,11 +8,15 @@
namespace Tegra {
namespace Engines {
-namespace Maxwell3D {
-void WriteReg(u32 method, u32 value);
+class Maxwell3D final {
+public:
+ Maxwell3D() = default;
+ ~Maxwell3D() = default;
-} // namespace Maxwell3D
+ /// Write the value to the register identified by method.
+ void WriteReg(u32 method, u32 value);
+};
} // namespace Engines
} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index c2134d63b..e4e5f9e5e 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -6,10 +6,8 @@
namespace Tegra {
namespace Engines {
-namespace MaxwellCompute {
-void WriteReg(u32 method, u32 value) {}
+void MaxwellCompute::WriteReg(u32 method, u32 value) {}
-} // namespace MaxwellCompute
} // namespace Engines
} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h
index dc9a13593..7262e1bcb 100644
--- a/src/video_core/engines/maxwell_compute.h
+++ b/src/video_core/engines/maxwell_compute.h
@@ -8,11 +8,15 @@
namespace Tegra {
namespace Engines {
-namespace MaxwellCompute {
-void WriteReg(u32 method, u32 value);
+class MaxwellCompute final {
+public:
+ MaxwellCompute() = default;
+ ~MaxwellCompute() = default;
-} // namespace MaxwellCompute
+ /// Write the value to the register identified by method.
+ void WriteReg(u32 method, u32 value);
+};
} // namespace Engines
} // namespace Tegra