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-rw-r--r--src/citra_qt/bootmanager.cpp3
-rw-r--r--src/citra_qt/main.cpp3
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp200
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp64
-rw-r--r--src/video_core/pica.h4
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.cpp52
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.h19
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer_cache.cpp25
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer_cache.h7
-rw-r--r--src/video_core/renderer_opengl/gl_resource_manager.h24
-rw-r--r--src/video_core/renderer_opengl/gl_state.cpp20
-rw-r--r--src/video_core/renderer_opengl/gl_state.h2
-rw-r--r--src/video_core/renderer_opengl/pica_to_gl.h10
13 files changed, 265 insertions, 168 deletions
diff --git a/src/citra_qt/bootmanager.cpp b/src/citra_qt/bootmanager.cpp
index d9bacfc3d..9aec16506 100644
--- a/src/citra_qt/bootmanager.cpp
+++ b/src/citra_qt/bootmanager.cpp
@@ -72,6 +72,9 @@ void EmuThread::run() {
}
}
+ // Shutdown the core emulation
+ System::Shutdown();
+
MicroProfileOnThreadExit();
render_window->moveContext();
diff --git a/src/citra_qt/main.cpp b/src/citra_qt/main.cpp
index 7fb1b0dcb..11813a2a8 100644
--- a/src/citra_qt/main.cpp
+++ b/src/citra_qt/main.cpp
@@ -283,9 +283,6 @@ void GMainWindow::ShutdownGame() {
emu_thread->wait();
emu_thread = nullptr;
- // Shutdown the core emulation
- System::Shutdown();
-
// Update the GUI
ui.action_Start->setEnabled(false);
ui.action_Start->setText(tr("Start"));
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 0fddb07a0..fbd6f94f9 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3908,7 +3908,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
ADC_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
adc_inst* const inst_cream = (adc_inst*)inst_base->component;
u32 rn_val = RN;
@@ -3943,7 +3943,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
ADD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
add_inst* const inst_cream = (add_inst*)inst_base->component;
u32 rn_val = RN;
@@ -3978,7 +3978,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
AND_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
and_inst* const inst_cream = (and_inst*)inst_base->component;
u32 lop = RN;
@@ -4012,7 +4012,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
BBL_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
bbl_inst *inst_cream = (bbl_inst *)inst_base->component;
if (inst_cream->L) {
LINK_RTN_ADDR;
@@ -4028,7 +4028,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
BIC_INST:
{
bic_inst *inst_cream = (bic_inst *)inst_base->component;
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
u32 lop = RN;
if (inst_cream->Rn == 15) {
lop += 2 * cpu->GetInstructionSize();
@@ -4058,7 +4058,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
BKPT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
}
@@ -4070,7 +4070,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
BLX_INST:
{
blx_inst *inst_cream = (blx_inst *)inst_base->component;
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
unsigned int inst = inst_cream->inst;
if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
@@ -4105,7 +4105,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
//
// This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
bx_inst* const inst_cream = (bx_inst*)inst_base->component;
u32 address = RM;
@@ -4126,7 +4126,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
CDP_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
// Undefined instruction here
cpu->NumInstrsToExecute = 0;
return num_instrs;
@@ -4147,7 +4147,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
CLZ_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
clz_inst* inst_cream = (clz_inst*)inst_base->component;
RD = clz(RM);
}
@@ -4158,7 +4158,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
CMN_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
cmn_inst* const inst_cream = (cmn_inst*)inst_base->component;
u32 rn_val = RN;
@@ -4181,7 +4181,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
CMP_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
cmp_inst* const inst_cream = (cmp_inst*)inst_base->component;
u32 rn_val = RN;
@@ -4236,7 +4236,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
CPY_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mov_inst* inst_cream = (mov_inst*)inst_base->component;
RD = SHIFTER_OPERAND;
@@ -4252,7 +4252,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
EOR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
eor_inst* inst_cream = (eor_inst*)inst_base->component;
u32 lop = RN;
@@ -4293,7 +4293,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDM_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4365,7 +4365,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SXTH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sxth_inst* inst_cream = (sxth_inst*)inst_base->component;
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
@@ -4426,7 +4426,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
UXTH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
}
@@ -4437,7 +4437,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
UXTAH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component;
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
@@ -4450,7 +4450,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4468,7 +4468,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRBT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4486,7 +4486,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
// Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0)
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4506,7 +4506,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
LDREX_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int read_addr = RN;
@@ -4525,7 +4525,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDREXB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int read_addr = RN;
@@ -4544,7 +4544,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDREXH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int read_addr = RN;
@@ -4563,7 +4563,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDREXD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int read_addr = RN;
@@ -4584,7 +4584,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4601,7 +4601,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRSB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
unsigned int value = Memory::Read8(addr);
@@ -4621,7 +4621,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRSH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4642,7 +4642,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
LDRT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -4661,7 +4661,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
MCR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mcr_inst* inst_cream = (mcr_inst*)inst_base->component;
unsigned int inst = inst_cream->inst;
@@ -4682,7 +4682,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
{
// Stubbed, as the MPCore doesn't have any registers that are accessible
// through this instruction.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
@@ -4697,7 +4697,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
MLA_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mla_inst* inst_cream = (mla_inst*)inst_base->component;
u64 rm = RM;
@@ -4721,7 +4721,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
MOV_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mov_inst* inst_cream = (mov_inst*)inst_base->component;
RD = SHIFTER_OPERAND;
@@ -4748,7 +4748,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
MRC_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
unsigned int inst = inst_cream->inst;
@@ -4775,7 +4775,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
{
// Stubbed, as the MPCore doesn't have any registers that are accessible
// through this instruction.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
@@ -4790,7 +4790,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
MRS_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mrs_inst* inst_cream = (mrs_inst*)inst_base->component;
if (inst_cream->R) {
@@ -4807,7 +4807,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
MSR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
msr_inst* inst_cream = (msr_inst*)inst_base->component;
const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
unsigned int inst = inst_cream->inst;
@@ -4851,7 +4851,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
MUL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mul_inst* inst_cream = (mul_inst*)inst_base->component;
u64 rm = RM;
@@ -4873,7 +4873,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
MVN_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mvn_inst* const inst_cream = (mvn_inst*)inst_base->component;
RD = ~SHIFTER_OPERAND;
@@ -4901,7 +4901,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
ORR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
orr_inst* const inst_cream = (orr_inst*)inst_base->component;
u32 lop = RN;
@@ -4944,7 +4944,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
PKHBT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000);
}
@@ -4956,7 +4956,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
PKHTB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
int shift_imm = inst_cream->imm ? inst_cream->imm : 31;
RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000);
@@ -4982,7 +4982,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
QDSUB_INST:
QSUB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u8 op1 = inst_cream->op1;
const u32 rm_val = RM;
@@ -5057,7 +5057,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
QSUB16_INST:
QSUBADDX_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u16 rm_lo = (RM & 0xFFFF);
const u16 rm_hi = ((RM >> 16) & 0xFFFF);
@@ -5117,7 +5117,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
REVSH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
rev_inst* const inst_cream = (rev_inst*)inst_base->component;
const u8 op1 = inst_cream->op1;
@@ -5162,7 +5162,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
RSB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
rsb_inst* const inst_cream = (rsb_inst*)inst_base->component;
u32 rn_val = RN;
@@ -5197,7 +5197,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
RSC_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
rsc_inst* const inst_cream = (rsc_inst*)inst_base->component;
u32 rn_val = RN;
@@ -5238,7 +5238,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SSUBADDX_INST:
SSUB16_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u8 op2 = inst_cream->op2;
@@ -5341,7 +5341,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SBC_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sbc_inst* const inst_cream = (sbc_inst*)inst_base->component;
u32 rn_val = RN;
@@ -5377,7 +5377,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SEL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u32 to = RM;
@@ -5436,7 +5436,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SEV_INST:
{
// Stubbed, as SEV is a hint instruction.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "SEV executed.");
}
@@ -5453,7 +5453,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SHSUB16_INST:
SHSUBADDX_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u8 op2 = inst_cream->op2;
@@ -5520,7 +5520,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMLA_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smla_inst* inst_cream = (smla_inst*)inst_base->component;
s32 operand1, operand2;
if (inst_cream->x == 0)
@@ -5548,7 +5548,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMUAD_INST:
SMUSD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
const u8 op2 = inst_cream->op2;
@@ -5601,7 +5601,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMLAL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
long long int rm = RM;
long long int rs = RS;
@@ -5630,7 +5630,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMLALXY_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
u64 operand1 = RN;
@@ -5660,7 +5660,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMLAW_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
const u32 rm_val = RM;
@@ -5686,7 +5686,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMLALD_INST:
SMLSLD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smlald_inst* const inst_cream = (smlald_inst*)inst_base->component;
const bool do_swap = (inst_cream->swap == 1);
@@ -5725,7 +5725,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMMLS_INST:
SMMUL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
const u32 rm_val = RM;
@@ -5759,7 +5759,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMUL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smul_inst* inst_cream = (smul_inst*)inst_base->component;
u32 operand1, operand2;
if (inst_cream->x == 0)
@@ -5780,7 +5780,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SMULL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
umull_inst* inst_cream = (umull_inst*)inst_base->component;
s64 rm = RM;
s64 rs = RS;
@@ -5807,7 +5807,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SMULW_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF);
@@ -5840,7 +5840,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SSAT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
u8 shift_type = inst_cream->shift_type;
@@ -5873,7 +5873,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SSAT16_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
const u8 saturate_to = inst_cream->sat_imm;
@@ -5904,7 +5904,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STM_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
unsigned int inst = inst_cream->inst;
@@ -5962,7 +5962,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SXTB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component;
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
@@ -5980,7 +5980,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -5999,7 +5999,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
UXTB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component;
RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
}
@@ -6010,7 +6010,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
UXTAB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component;
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
@@ -6023,7 +6023,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STRB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
@@ -6036,7 +6036,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STRBT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
@@ -6049,7 +6049,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STRD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -6065,7 +6065,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STREX_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
@@ -6085,7 +6085,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STREXB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
@@ -6105,7 +6105,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STREXD_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
@@ -6136,7 +6136,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STREXH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
unsigned int write_addr = cpu->Reg[inst_cream->Rn];
@@ -6156,7 +6156,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STRH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -6170,7 +6170,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
STRT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
inst_cream->get_addr(cpu, inst_cream->inst, addr);
@@ -6184,7 +6184,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SUB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sub_inst* const inst_cream = (sub_inst*)inst_base->component;
u32 rn_val = RN;
@@ -6219,7 +6219,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SWI_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
swi_inst* const inst_cream = (swi_inst*)inst_base->component;
SVC::CallSVC(inst_cream->num & 0xFFFF);
}
@@ -6231,7 +6231,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SWP_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
swp_inst* inst_cream = (swp_inst*)inst_base->component;
addr = RN;
@@ -6247,7 +6247,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SWPB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
swp_inst* inst_cream = (swp_inst*)inst_base->component;
addr = RN;
unsigned int value = Memory::Read8(addr);
@@ -6261,7 +6261,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
SXTAB_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component;
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
@@ -6279,7 +6279,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SXTAB16_INST:
SXTB16_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component;
const u8 rotation = inst_cream->rotate * 8;
@@ -6311,7 +6311,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
SXTAH_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component;
unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
@@ -6327,7 +6327,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
TEQ_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
teq_inst* const inst_cream = (teq_inst*)inst_base->component;
u32 lop = RN;
@@ -6349,7 +6349,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
TST_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
tst_inst* const inst_cream = (tst_inst*)inst_base->component;
u32 lop = RN;
@@ -6377,7 +6377,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
USUB16_INST:
USUBADDX_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u8 op2 = inst_cream->op2;
@@ -6548,7 +6548,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
UHSUB8_INST:
UHSUB16_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u32 rm_val = RM;
const u32 rn_val = RN;
@@ -6623,7 +6623,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
UMAAL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
umaal_inst* const inst_cream = (umaal_inst*)inst_base->component;
const u64 rm = RM;
const u64 rn = RN;
@@ -6641,7 +6641,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
UMLAL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
unsigned long long int rm = RM;
unsigned long long int rs = RS;
@@ -6664,7 +6664,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
}
UMULL_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
umull_inst* inst_cream = (umull_inst*)inst_base->component;
unsigned long long int rm = RM;
unsigned long long int rs = RS;
@@ -6738,7 +6738,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
UQSUB16_INST:
UQSUBADDX_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
const u8 op2 = inst_cream->op2;
@@ -6795,7 +6795,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
USAD8_INST:
USADA8_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
const u8 ra_idx = inst_cream->Ra;
@@ -6824,7 +6824,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
USAT_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
u8 shift_type = inst_cream->shift_type;
@@ -6857,7 +6857,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
USAT16_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
const u8 saturate_to = inst_cream->sat_imm;
@@ -6880,7 +6880,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
UXTAB16_INST:
UXTB16_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component;
const u8 rn_idx = inst_cream->Rn;
@@ -6911,7 +6911,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
WFE_INST:
{
// Stubbed, as WFE is a hint instruction.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "WFE executed.");
}
@@ -6924,7 +6924,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
WFI_INST:
{
// Stubbed, as WFI is a hint instruction.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "WFI executed.");
}
@@ -6937,7 +6937,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
YIELD_INST:
{
// Stubbed, as YIELD is a hint instruction.
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
LOG_TRACE(Core_ARM11, "YIELD executed.");
}
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 49298d7ba..4f9083515 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -37,7 +37,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMLA_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmla_inst *inst_cream = (vmla_inst *)inst_base->component;
@@ -86,7 +86,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMLS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmls_inst *inst_cream = (vmls_inst *)inst_base->component;
@@ -135,7 +135,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VNMLA_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component;
@@ -185,7 +185,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VNMLS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component;
@@ -234,7 +234,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VNMUL_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component;
@@ -283,7 +283,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMUL_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmul_inst *inst_cream = (vmul_inst *)inst_base->component;
@@ -332,7 +332,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VADD_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vadd_inst *inst_cream = (vadd_inst *)inst_base->component;
@@ -381,7 +381,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VSUB_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vsub_inst *inst_cream = (vsub_inst *)inst_base->component;
@@ -430,7 +430,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VDIV_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component;
@@ -485,7 +485,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMOVI_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovi_inst *inst_cream = (vmovi_inst *)inst_base->component;
@@ -529,7 +529,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMOVR_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovr_inst *inst_cream = (vmovr_inst *)inst_base->component;
@@ -571,7 +571,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vabs)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VABS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vabs_inst *inst_cream = (vabs_inst *)inst_base->component;
@@ -621,7 +621,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vneg)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VNEG_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vneg_inst *inst_cream = (vneg_inst *)inst_base->component;
@@ -670,7 +670,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VSQRT_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component;
@@ -719,7 +719,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VCMP_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component;
@@ -768,7 +768,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VCMP2_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component;
@@ -817,7 +817,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VCVTBDS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component;
@@ -868,7 +868,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VCVTBFF_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component;
@@ -917,7 +917,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VCVTBFI_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component;
@@ -974,7 +974,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMOVBRS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovbrs_inst *inst_cream = (vmovbrs_inst *)inst_base->component;
@@ -1017,7 +1017,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMSR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled ,
and in privileged mode */
/* Exceptions must be checked, according to v7 ref manual */
@@ -1083,7 +1083,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMOVBRC_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovbrc_inst* const inst_cream = (vmovbrc_inst*)inst_base->component;
@@ -1126,7 +1126,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMRS_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled,
and in privileged mode */
/* Exceptions must be checked, according to v7 ref manual */
@@ -1214,7 +1214,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMOVBCR_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovbcr_inst* const inst_cream = (vmovbcr_inst*) inst_base->component;
@@ -1266,7 +1266,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int inde
#ifdef VFP_INTERPRETER_IMPL
VMOVBRRSS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovbrrss_inst* const inst_cream = (vmovbrrss_inst*)inst_base->component;
@@ -1314,7 +1314,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index
#ifdef VFP_INTERPRETER_IMPL
VMOVBRRD_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component;
@@ -1368,7 +1368,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VSTR_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vstr_inst *inst_cream = (vstr_inst *)inst_base->component;
@@ -1433,7 +1433,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VPUSH_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vpush_inst *inst_cream = (vpush_inst *)inst_base->component;
@@ -1511,7 +1511,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VSTM_INST: /* encoding 1 */
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vstm_inst* inst_cream = (vstm_inst*)inst_base->component;
@@ -1593,7 +1593,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VPOP_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vpop_inst *inst_cream = (vpop_inst *)inst_base->component;
@@ -1667,7 +1667,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VLDR_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vldr_inst *inst_cream = (vldr_inst *)inst_base->component;
@@ -1738,7 +1738,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VLDM_INST:
{
- if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
vldm_inst* inst_cream = (vldm_inst*)inst_base->component;
diff --git a/src/video_core/pica.h b/src/video_core/pica.h
index 855cb442e..c1dca5087 100644
--- a/src/video_core/pica.h
+++ b/src/video_core/pica.h
@@ -135,6 +135,7 @@ struct Regs {
};
union {
+ u32 raw;
BitField< 0, 8, u32> r;
BitField< 8, 8, u32> g;
BitField<16, 8, u32> b;
@@ -339,6 +340,7 @@ struct Regs {
};
union {
+ u32 const_color;
BitField< 0, 8, u32> const_r;
BitField< 8, 8, u32> const_g;
BitField<16, 8, u32> const_b;
@@ -389,6 +391,7 @@ struct Regs {
TevStageConfig tev_stage5;
union {
+ u32 raw;
BitField< 0, 8, u32> r;
BitField< 8, 8, u32> g;
BitField<16, 8, u32> b;
@@ -473,6 +476,7 @@ struct Regs {
};
union {
+ u32 raw;
BitField< 0, 8, u32> r;
BitField< 8, 8, u32> g;
BitField<16, 8, u32> b;
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index 80e773728..0260a28ce 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -68,6 +68,12 @@ void RasterizerOpenGL::InitObjects() {
uniform_tev_cfg.updates_combiner_buffer_color_alpha = glGetUniformLocation(shader.handle, (tev_ref_str + ".updates_combiner_buffer_color_alpha").c_str());
}
+ // Create sampler objects
+ for (int i = 0; i < texture_samplers.size(); ++i) {
+ texture_samplers[i].Create();
+ state.texture_units[i].sampler = texture_samplers[i].sampler.handle;
+ }
+
// Generate VBO and VAO
vertex_buffer.Create();
vertex_array.Create();
@@ -445,6 +451,45 @@ void RasterizerOpenGL::NotifyFlush(PAddr addr, u32 size) {
res_cache.NotifyFlush(addr, size);
}
+void RasterizerOpenGL::SamplerInfo::Create() {
+ sampler.Create();
+ mag_filter = min_filter = TextureConfig::Linear;
+ wrap_s = wrap_t = TextureConfig::Repeat;
+ border_color = 0;
+
+ glSamplerParameteri(sampler.handle, GL_TEXTURE_MIN_FILTER, GL_LINEAR); // default is GL_LINEAR_MIPMAP_LINEAR
+ // Other attributes have correct defaults
+}
+
+void RasterizerOpenGL::SamplerInfo::SyncWithConfig(const Pica::Regs::TextureConfig& config) {
+ GLuint s = sampler.handle;
+
+ if (mag_filter != config.mag_filter) {
+ mag_filter = config.mag_filter;
+ glSamplerParameteri(s, GL_TEXTURE_MAG_FILTER, PicaToGL::TextureFilterMode(mag_filter));
+ }
+ if (min_filter != config.min_filter) {
+ min_filter = config.min_filter;
+ glSamplerParameteri(s, GL_TEXTURE_MIN_FILTER, PicaToGL::TextureFilterMode(min_filter));
+ }
+
+ if (wrap_s != config.wrap_s) {
+ wrap_s = config.wrap_s;
+ glSamplerParameteri(s, GL_TEXTURE_WRAP_S, PicaToGL::WrapMode(wrap_s));
+ }
+ if (wrap_t != config.wrap_t) {
+ wrap_t = config.wrap_t;
+ glSamplerParameteri(s, GL_TEXTURE_WRAP_T, PicaToGL::WrapMode(wrap_t));
+ }
+
+ if (wrap_s == TextureConfig::ClampToBorder || wrap_t == TextureConfig::ClampToBorder) {
+ if (border_color != config.border_color.raw) {
+ auto gl_color = PicaToGL::ColorRGBA8(border_color);
+ glSamplerParameterfv(s, GL_TEXTURE_BORDER_COLOR, gl_color.data());
+ }
+ }
+}
+
void RasterizerOpenGL::ReconfigureColorTexture(TextureInfo& texture, Pica::Regs::ColorFormat format, u32 width, u32 height) {
GLint internal_format;
@@ -658,7 +703,7 @@ void RasterizerOpenGL::SyncBlendFuncs() {
}
void RasterizerOpenGL::SyncBlendColor() {
- auto blend_color = PicaToGL::ColorRGBA8((u8*)&Pica::g_state.regs.output_merger.blend_const.r);
+ auto blend_color = PicaToGL::ColorRGBA8(Pica::g_state.regs.output_merger.blend_const.raw);
state.blend.color.red = blend_color[0];
state.blend.color.green = blend_color[1];
state.blend.color.blue = blend_color[2];
@@ -728,7 +773,7 @@ void RasterizerOpenGL::SyncTevOps(unsigned stage_index, const Pica::Regs::TevSta
}
void RasterizerOpenGL::SyncTevColor(unsigned stage_index, const Pica::Regs::TevStageConfig& config) {
- auto const_color = PicaToGL::ColorRGBA8((u8*)&config.const_r);
+ auto const_color = PicaToGL::ColorRGBA8(config.const_color);
glUniform4fv(uniform_tev_cfgs[stage_index].const_color, 1, const_color.data());
}
@@ -737,7 +782,7 @@ void RasterizerOpenGL::SyncTevMultipliers(unsigned stage_index, const Pica::Regs
}
void RasterizerOpenGL::SyncCombinerColor() {
- auto combiner_color = PicaToGL::ColorRGBA8((u8*)&Pica::g_state.regs.tev_combiner_buffer_color.r);
+ auto combiner_color = PicaToGL::ColorRGBA8(Pica::g_state.regs.tev_combiner_buffer_color.raw);
glUniform4fv(uniform_tev_combiner_buffer_color, 1, combiner_color.data());
}
@@ -772,6 +817,7 @@ void RasterizerOpenGL::SyncDrawState() {
const auto& texture = pica_textures[texture_index];
if (texture.enabled) {
+ texture_samplers[texture_index].SyncWithConfig(texture.config);
res_cache.LoadAndBindTexture(state, texture_index, texture);
} else {
state.texture_units[texture_index].texture_2d = 0;
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.h b/src/video_core/renderer_opengl/gl_rasterizer.h
index a02d5c856..24560d7f8 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.h
+++ b/src/video_core/renderer_opengl/gl_rasterizer.h
@@ -80,6 +80,24 @@ private:
GLenum gl_type;
};
+ struct SamplerInfo {
+ using TextureConfig = Pica::Regs::TextureConfig;
+
+ OGLSampler sampler;
+
+ /// Creates the sampler object, initializing its state so that it's in sync with the SamplerInfo struct.
+ void Create();
+ /// Syncs the sampler object with the config, updating any necessary state.
+ void SyncWithConfig(const TextureConfig& config);
+
+ private:
+ TextureConfig::TextureFilter mag_filter;
+ TextureConfig::TextureFilter min_filter;
+ TextureConfig::WrapMode wrap_s;
+ TextureConfig::WrapMode wrap_t;
+ u32 border_color;
+ };
+
/// Structure that the hardware rendered vertices are composed of
struct HardwareVertex {
HardwareVertex(const Pica::Shader::OutputVertex& v) {
@@ -193,6 +211,7 @@ private:
PAddr last_fb_depth_addr;
// Hardware rasterizer
+ std::array<SamplerInfo, 3> texture_samplers;
TextureInfo fb_color_texture;
DepthTextureInfo fb_depth_texture;
OGLShader shader;
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
index 1e38c2e6d..d9ccf2a3f 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.cpp
@@ -20,9 +20,8 @@ RasterizerCacheOpenGL::~RasterizerCacheOpenGL() {
MICROPROFILE_DEFINE(OpenGL_TextureUpload, "OpenGL", "Texture Upload", MP_RGB(128, 64, 192));
-void RasterizerCacheOpenGL::LoadAndBindTexture(OpenGLState &state, unsigned texture_unit, const Pica::Regs::FullTextureConfig& config) {
- PAddr texture_addr = config.config.GetPhysicalAddress();
- const auto cached_texture = texture_cache.find(texture_addr);
+void RasterizerCacheOpenGL::LoadAndBindTexture(OpenGLState &state, unsigned texture_unit, const Pica::DebugUtils::TextureInfo& info) {
+ const auto cached_texture = texture_cache.find(info.physical_address);
if (cached_texture != texture_cache.end()) {
state.texture_units[texture_unit].texture_2d = cached_texture->second->texture.handle;
@@ -37,26 +36,12 @@ void RasterizerCacheOpenGL::LoadAndBindTexture(OpenGLState &state, unsigned text
state.Apply();
glActiveTexture(GL_TEXTURE0 + texture_unit);
- glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, PicaToGL::TextureFilterMode(config.config.mag_filter));
- glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, PicaToGL::TextureFilterMode(config.config.min_filter));
-
- GLenum wrap_s = PicaToGL::WrapMode(config.config.wrap_s);
- GLenum wrap_t = PicaToGL::WrapMode(config.config.wrap_t);
- glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, wrap_s);
- glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, wrap_t);
-
- if (wrap_s == GL_CLAMP_TO_BORDER || wrap_t == GL_CLAMP_TO_BORDER) {
- auto border_color = PicaToGL::ColorRGBA8((u8*)&config.config.border_color.r);
- glTexParameterfv(GL_TEXTURE_2D, GL_TEXTURE_BORDER_COLOR, border_color.data());
- }
-
- const auto info = Pica::DebugUtils::TextureInfo::FromPicaRegister(config.config, config.format);
- u8* texture_src_data = Memory::GetPhysicalPointer(texture_addr);
+ u8* texture_src_data = Memory::GetPhysicalPointer(info.physical_address);
new_texture->width = info.width;
new_texture->height = info.height;
new_texture->size = info.stride * info.height;
- new_texture->addr = texture_addr;
+ new_texture->addr = info.physical_address;
new_texture->hash = Common::ComputeHash64(texture_src_data, new_texture->size);
std::unique_ptr<Math::Vec4<u8>[]> temp_texture_buffer_rgba(new Math::Vec4<u8>[info.width * info.height]);
@@ -69,7 +54,7 @@ void RasterizerCacheOpenGL::LoadAndBindTexture(OpenGLState &state, unsigned text
glTexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, info.width, info.height, 0, GL_RGBA, GL_UNSIGNED_BYTE, temp_texture_buffer_rgba.get());
- texture_cache.emplace(texture_addr, std::move(new_texture));
+ texture_cache.emplace(info.physical_address, std::move(new_texture));
}
}
diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.h b/src/video_core/renderer_opengl/gl_rasterizer_cache.h
index d8f9edf59..ec56237b5 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer_cache.h
+++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.h
@@ -6,6 +6,7 @@
#include "gl_state.h"
#include "gl_resource_manager.h"
+#include "video_core/debug_utils/debug_utils.h"
#include "video_core/pica.h"
#include <memory>
@@ -16,7 +17,11 @@ public:
~RasterizerCacheOpenGL();
/// Loads a texture from 3DS memory to OpenGL and caches it (if not already cached)
- void LoadAndBindTexture(OpenGLState &state, unsigned texture_unit, const Pica::Regs::FullTextureConfig& config);
+ void LoadAndBindTexture(OpenGLState &state, unsigned texture_unit, const Pica::DebugUtils::TextureInfo& info);
+
+ void LoadAndBindTexture(OpenGLState &state, unsigned texture_unit, const Pica::Regs::FullTextureConfig& config) {
+ LoadAndBindTexture(state, texture_unit, Pica::DebugUtils::TextureInfo::FromPicaRegister(config.config, config.format));
+ }
/// Flush any cached resource that touches the flushed region
void NotifyFlush(PAddr addr, u32 size, bool ignore_hash = false);
diff --git a/src/video_core/renderer_opengl/gl_resource_manager.h b/src/video_core/renderer_opengl/gl_resource_manager.h
index 68fc1e6d3..65034d40d 100644
--- a/src/video_core/renderer_opengl/gl_resource_manager.h
+++ b/src/video_core/renderer_opengl/gl_resource_manager.h
@@ -37,6 +37,30 @@ public:
GLuint handle = 0;
};
+class OGLSampler : private NonCopyable {
+public:
+ OGLSampler() = default;
+ OGLSampler(OGLSampler&& o) { std::swap(handle, o.handle); }
+ ~OGLSampler() { Release(); }
+ OGLSampler& operator=(OGLSampler&& o) { std::swap(handle, o.handle); return *this; }
+
+ /// Creates a new internal OpenGL resource and stores the handle
+ void Create() {
+ if (handle != 0) return;
+ glGenSamplers(1, &handle);
+ }
+
+ /// Deletes the internal OpenGL resource
+ void Release() {
+ if (handle == 0) return;
+ glDeleteSamplers(1, &handle);
+ OpenGLState::ResetSampler(handle);
+ handle = 0;
+ }
+
+ GLuint handle = 0;
+};
+
class OGLShader : private NonCopyable {
public:
OGLShader() = default;
diff --git a/src/video_core/renderer_opengl/gl_state.cpp b/src/video_core/renderer_opengl/gl_state.cpp
index ba47ce8b8..e02c27fbf 100644
--- a/src/video_core/renderer_opengl/gl_state.cpp
+++ b/src/video_core/renderer_opengl/gl_state.cpp
@@ -44,6 +44,7 @@ OpenGLState::OpenGLState() {
for (auto& texture_unit : texture_units) {
texture_unit.texture_2d = 0;
+ texture_unit.sampler = 0;
}
draw.framebuffer = 0;
@@ -154,10 +155,13 @@ void OpenGLState::Apply() {
}
// Textures
- for (unsigned texture_index = 0; texture_index < ARRAY_SIZE(texture_units); ++texture_index) {
- if (texture_units[texture_index].texture_2d != cur_state.texture_units[texture_index].texture_2d) {
- glActiveTexture(GL_TEXTURE0 + texture_index);
- glBindTexture(GL_TEXTURE_2D, texture_units[texture_index].texture_2d);
+ for (unsigned i = 0; i < ARRAY_SIZE(texture_units); ++i) {
+ if (texture_units[i].texture_2d != cur_state.texture_units[i].texture_2d) {
+ glActiveTexture(GL_TEXTURE0 + i);
+ glBindTexture(GL_TEXTURE_2D, texture_units[i].texture_2d);
+ }
+ if (texture_units[i].sampler != cur_state.texture_units[i].sampler) {
+ glBindSampler(i, texture_units[i].sampler);
}
}
@@ -192,6 +196,14 @@ void OpenGLState::ResetTexture(GLuint id) {
}
}
+void OpenGLState::ResetSampler(GLuint id) {
+ for (auto& unit : cur_state.texture_units) {
+ if (unit.sampler == id) {
+ unit.sampler = 0;
+ }
+ }
+}
+
void OpenGLState::ResetProgram(GLuint id) {
if (cur_state.draw.shader_program == id) {
cur_state.draw.shader_program = 0;
diff --git a/src/video_core/renderer_opengl/gl_state.h b/src/video_core/renderer_opengl/gl_state.h
index 43aa29a81..6ecbedbb4 100644
--- a/src/video_core/renderer_opengl/gl_state.h
+++ b/src/video_core/renderer_opengl/gl_state.h
@@ -57,6 +57,7 @@ public:
// 3 texture units - one for each that is used in PICA fragment shader emulation
struct {
GLuint texture_2d; // GL_TEXTURE_BINDING_2D
+ GLuint sampler; // GL_SAMPLER_BINDING
} texture_units[3];
struct {
@@ -77,6 +78,7 @@ public:
void Apply();
static void ResetTexture(GLuint id);
+ static void ResetSampler(GLuint id);
static void ResetProgram(GLuint id);
static void ResetBuffer(GLuint id);
static void ResetVertexArray(GLuint id);
diff --git a/src/video_core/renderer_opengl/pica_to_gl.h b/src/video_core/renderer_opengl/pica_to_gl.h
index 6344f467f..04c1d1a34 100644
--- a/src/video_core/renderer_opengl/pica_to_gl.h
+++ b/src/video_core/renderer_opengl/pica_to_gl.h
@@ -175,11 +175,11 @@ inline GLenum StencilOp(Pica::Regs::StencilAction action) {
return stencil_op_table[(unsigned)action];
}
-inline std::array<GLfloat, 4> ColorRGBA8(const u8* bytes) {
- return { { bytes[0] / 255.0f,
- bytes[1] / 255.0f,
- bytes[2] / 255.0f,
- bytes[3] / 255.0f
+inline std::array<GLfloat, 4> ColorRGBA8(const u32 color) {
+ return { { (color >> 0 & 0xFF) / 255.0f,
+ (color >> 8 & 0xFF) / 255.0f,
+ (color >> 16 & 0xFF) / 255.0f,
+ (color >> 24 & 0xFF) / 255.0f
} };
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 16:57:53 +0100