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2018-07-30externals: Update dynarmic to 73d3efcMerryMage1-0/+0
73d3efc emit_x64_floating_point: Deduplicate code c9508c3 fuzz_with_unicorn: Randomize FPCR.DN 2970833 emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1 150764f emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1 b7d209c IR: SSE4.1 implementation of FPVectorRoundInt 8cf8270 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant 8f46c26 IR: Initial implementation of FPVectorRoundInt 97017bb A64: Implement SQADD and SQSUB, scalar variant ce58863 IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths e80f8ff a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument 1e4ec7e simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function 6f9dc9b A64: Implement SMAXP, SMINP, UMAXP, UMINP 1dfb29f ir: Add opcodes for vector paired maximum and minimums 017b510 A64: Implement SMAXV, SMINV, UMAXV, and UMINV aae22ee ir: Add opcodes for performing scalar integral min/max 6ef3af3 A64: Implement PMULL{2} 2a4ce19 translate: Deduplicate GetDataSize() functions 0e01500 floating_point_{conditional}_compare: Deduplicate code 259237c common: Move all cryptographic function to common/crypto c5f1080 a32_emit_x64: BMI2 implementation of A32SetCpsr a23304a a32_emit_x64: Shorten EmitA32GetCpsr 57604d2 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid 945fa48 A64: Implement PMUL 656a404 ir: Add opcode for performing polynomial multiplication 05143df A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant 34ce767 A64: Implement FCVTZS (vector, integer), single/double variant 0f9bc2d IR: Implement FPVectorTo{Signed,Unsigned}Fixed 0189e44 fp/info: Replace constant value generators with FPValue db16568 emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min} 31148bd emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs 4c3ca51 A64: Implement FMAX's vector single and double precision variants bf0f21c A64: Implement FMIN's vector single and double precision variants 76f0ca0 IR: Implement FPVector{Max,Min} 6c37c31 FPRecipEstimate: Move offset out of function 59546f3 microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits 3f6b03a A64: Implement FRECPS, vector/scalar single/double variants 2d2ca5e IR: Implement FPRecipStepFused, FPVectorRecipStepFused 5cb9f1d A64: Implement FRECPE, vector single/double variant c5a14ab IR: Implement FPVectorRecipEstimate 56f8a0b A64: Implement FRECPE, scalar single/double variant fde69b4 IR: Implement FPRecipEstimate 186e52c IR: Implement FPRecipEstimate cf2e1ae fp: Change FPUnpacked to a normalized representation
2018-07-25externals: Update dynarmic to 98e2380MerryMage1-0/+0
98e2380 fuzz_with_unicorn: Disable testing of FDIV 041b7d5 block_of_code: Add ABI_PARAMS array 2a2371c A64: Implement MLA, MLS (by element), vector single/double variant 78c640a A64: Implement FMLS (vector), single/double variant b6b6993 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly 4b9d12a emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused b1e3616 IR: Implement FPVectorNeg 4343612 A64: Implement FMLA (vector), single/double variant 93eeb25 IR: Implement FPVectorMulAdd 57e5c7e emit_x64_vector_floating_point: Standardize naming scheme bcb9e41 emit_x64_floating_point: Simplify indexers 83aa585 emit_x64_vector_floating_point: Simplify EmitVectorOperation* f4087c8 mp: rename mp.h to mp/function_info.h 1864090 emit_x64_vector: Slightly improve ArithmeticShiftRightByte e048441 emit_x64_vector: Simplify VectorShuffleImpl ff025e8 IR: Implement A64OrQC 6fac68d A64: Implement UQSHRN, UQRSHRN (vector) 5a8d9c3 emit_x64_vector: -0x80000000 isn't -0x80000000 759289e A64: Implement UQXTN (vector) 2a96281 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison 0682353 A64: Implement SQXTN (vector) 6c5229e emit_x64_vector: packusdw reqiures SSE4.1 158d9b1 A64: Implement SQSHRUN, SQRSHRUN (vector) f886013 simd_shift_by_immediate: Simplify ShiftRight d9b59c6 A64: Implement SQXTUN 50fe28b microinstruction: Reorganize FPSCR related instruction queries d9d036a microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() db96163 u128: Make Bit() a const-qualified member function f7052ae A64: Implement FRSQRTS (vector), single/double variant 0925ef6 A64: Implement FRSQRTE (vector), single/double variant f4cbbe3 A64: Implement FRSQRTS (scalar), single/double variant 4ef864e IR: Implement FPRSqrtStepFused 9dffeeb fp: Implement FPRSqrtStepFused aa04556 fp: Implement FPNeg cbde1c5 process_nan: Add two operand variant 1ec2663 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant 027ddf9 emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation 75a9f77 fp: Use a forward declaration in fused.h 1ee1630 u128: Implement comparison operators in terms of one another 3b77f48 tests: Print cpu info bed3cc0 u128: StickyLogicalShiftRight requires special-casing for amount == 64 15d04f4 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 7cfccdf A64: Implement FMUL (by element)'s scalar double/single-precision variant 7d2d62e (fpmuladd) emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64} a599eac fp: Implement FPMulAdd d70b90e process_nan: Add FPProcessNaNs3 38ef0e0 block_of_code: Add SysV ABI fifth and sixth parameters 8e2ff56 u128: Add StickyLogicalShiftRight 3b337df u128: Add Multiply64To128 8219075 u128: Add u128::Bit a574dcb u128: Add comparison operators 391d6d4 unpacked: Use ResidualErrorOnRightShift in FPRoundBase 5e0cf9c fp: Remove MantissaT 8c0a84c FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate c41d855 FPRSqrtEstimate: Deduplicate array bounds 4cf055b A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV bf24f0f FPRSqrtEstimate: Use forward declarations where applicable 206230e translate: Return by bool in helpers where applicable 346b725 Simplify fallback case for EmitVectorSetElement64() 2c34e1d emit_x64_floating_point: s/Esimate/Estimate/ 5213fb6 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant 7ed089f IR: Implement FPRSqrtEstimate cd2e286 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant
2018-07-22externals: Update dynarmic to fc6b73bdMerryMage1-0/+0
Resolves issues: * 128-bit exclusive writes on Windows * Non-updating CNTPCT_EL0 fc6b73 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT 888c67 a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes 352d53 emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns() ab7fe7 A64: Implement SADDLV 09bd2b A64: Implement UADDLV 62e86d fp: Use forward declarations where applicable b3edb7 emit_x64_vector: Append 'v' prefix onto movq in AVX path
2018-07-21externals: Update dynarmic to 7ea1241Lioncash1-0/+0
Resolves an issue with TPIDR setting being erroneously removed in the dead code pass.
2018-07-19externals: Update dynarmic to 5a91c94.bunnei1-0/+0
2018-07-15externals: Update dynarmic to dfdec79Lioncash1-0/+0
2018-07-07externals: Update dynarmic to f7d11baa1Lioncash1-0/+0
2018-05-23externals: Update dynarmicLioncash1-0/+0
Updates dynarmic to revision 990a569b7a5f2518fe08682f5ebf8536e5388d66
2018-04-28externals: Update dynarmicLioncash1-0/+0
Just a basic update to keep it in sync
2018-04-20externals: Update dynarmic to HEADLioncash1-0/+0
2018-03-29dynarmic: Update to 9cc12d8MerryMage1-0/+0
9cc12d8 abi: Missing includes ac35ad5 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64} 6f03fdd A64: system: Use an enum class for MRS/MSR register encodings
2018-03-27dynarmic: Update to 12a1020MerryMage1-0/+0
12a1020 emit_X64_floating_point: Near jmp to end instead of short jmp 6278f83 emit_x64_vector: Fix typo in VectorShuffleImpl 25a0204 A64: Implement REV64 aa92e33 bit_util: Do nothing in RotateRight if the rotation amount is zero e537985 A64: Implement REV32 (vector) f62a258 ir: Add IR opcodes for emitting vector shuffles 36ac6ec emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64 20a59a9 A64: Implement REV16 (vector) b2f7bb0 CMakeLists: Add fp_util, macro_util and math_util headers fd21b58 A64: Implement EOR3 and BCAX a48c0bb travis: Use yuzu's unicorn fork 59e62e0 externals: Update catch to v2.2.1
2018-02-21dynarmic: Update to 6b4c6b0MerryMage1-0/+0
6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-17updated dynarmicFernandoS271-0/+0
2018-02-12arm_dynarmic: Support direct page table accessMerryMage1-0/+0
2018-02-09dynarmic: Fix bug due to Windows ABI mismatchMerryMage1-0/+0
2018-02-09dynarmic: Update to 41ae12263MerryMage1-0/+0
Changes: Primarily implementing more A64 instructions
2018-01-21externals: Update dynarmicMerryMage1-0/+0
a6d17e A64: Implement AND (vector) 963453 tests/A64: Randomize vectors adcd34 tests/A64/unicorn: Print interrupt number when InterruptHook is hit 304c91 tests/A64: Allow RunTestInstance to start from an arbitrary offset d333b5 A64: Implement ADD (vector, vector) 1cf87a A64: Implement REV, REV32, and REV16 (#126) 9fc157 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 50c181 reg_alloc: GetBitWidth: Add UNREACHABLE adccbf reg_alloc: Consider bitwidth of data and registers when emitting instructions 7b7f23 A64: Implement CSEL 2f8413 IR: Implement Conditional Select ebb3e8 A64/tests: Split unicorn sanity checking from other tests 5740a0 tests/A64: Single random instruction: Test branch instructions as well 0892b4 A64/translate/branch: bug: Read-after-write error in BLR e77bc2 A64: Implement SBFM, BFM, UBFM 0c37ca A64: Implement MOVN, MOVZ, MOVK b6bb59 travis: Print current test information e77207 fuzz_thumb: Off by one error a04ca2 ir/location_descriptor: Add missing <functional> header for std::hash 1e0f5c travis: Run A64 tests
2018-01-13Update dynarmic to bc73004MerryMage1-0/+0
bc73004 a64_merge_interpret_blocks: Remove debug output 4e656ed tests/A64: Randomize PSTATE.<NZCV> fd9530b A64: Optimization: Merge interpret blocks 3c9eb04 testenv: Use format constants 324f3fc tests/A64: Unicorn interface fixes 98ecbe7 tests/A64: Fuzz against unicorn b1d38e7 tests/A64: Move TestEnvironment to own header 5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 edadeea A64 inferface: Use two argument static_assert 9ab1304 A64: Add ExceptionRaised IR instruction 6843eed Update readme 7438d07 A64/translate: Add TranslateSingleInstruction function
2018-01-12dynarmic: Update to 83afe435MerryMage1-0/+0
2018-01-12arm_dynarmic: Implement coreMerryMage1-0/+0
2018-01-04externals: Point dynarmic at a real commit.bunnei1-0/+0
2017-10-25externals: Update dynarmic and xbyak.bunnei1-0/+0
2017-06-17Stop using reserved operator names (and/or/xor) with XbyakYuri Kunde Schlesner1-0/+0
Also has the Dynarmic upgrade with the same change
2017-05-27Update dynarmicYuri Kunde Schlesner1-0/+0
Updated to incorporate fix from MerryMage/dynarmic#106 which is required for using fmt in Citra.
2017-02-21HW: add AES engine & implement AES-CCMwwylele1-0/+0
2017-02-18dynarmic: Update the submodule.Emmanuel Gil Peyrot1-0/+0
This fixes a build issue on gcc 6 due to -Werror and a warning caused by boost::optional, see: https://github.com/MerryMage/dynarmic/issues/83
2017-02-03arm_dynarmic: Update memory interfaceMerryMage1-0/+0
2017-02-03arm_dynarmic: CP15 supportMerryMage1-0/+0
2016-12-22arm_dynarmic: Provide MemoryReadCode callbackMerryMage1-0/+0
Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
2016-12-15externals: Update DynarmicYuri Kunde Schlesner1-0/+0
Required to be able to use Xbyak in Citra without header conflicts.
2016-12-05Dynarmic: Update dynarmic to versionSubv1-0/+0
54d051977f7a6af9c7596ba6a4e6eb467bd1e0bc dynarmic log: 54d0519 emit_x64: Use movdqa instead of movaps in EmitPackedSubU8 52e1445 Implement USUB8:33 2016 +0000 5c1aab1 Implement CLZ 1a1646d Implement UADD8 7cad694 IR: Implement new pseudo-operation GetGEFromOp 370f654 fuzz_arm: Add tests for parallel add/subtract (modulo) 25f21b5 emit_x64: Inline nzcv computation into EmitFPCompare32 and EmitFPCompare64 52fdec5 CMakeLists: Add support for LLVM on Windows cede5e4 emit_x64: Use xorps/xorpd when argument to TransferToFP32/TransferToFP64 is an immediate zero e166965 Implement VCMP2:33 2016 +0000 f2fe376 Support 64-bit immediates ff00b8c Document register allocator and return stack buffer optimization 95f34c6 reg_alloc: Remove unnecessary breaks after returns (#54) dc9707e externals: Update xbyak to 5.32 de1f831 microinstruction: Make use_count private (#53) 3621a92 reg_alloc: Register allocator related constraints belong with the rest of the register allocator
2016-11-30dynarmic: Fix ABI violationMerryMage1-0/+0
Caused by not saving/restoring the x64 r15 register on entry/exit from JITted code. Closes #2224.
2016-11-30Update dynarmic to the latest version (#2234)James Rowe1-0/+0
2016-09-15dynarmic: Add new submodule.bunnei1-0/+0
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