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2023-12-23kernel: instantiate memory separately for each guest processLiam1-1/+1
2023-12-04core: refactor emulated cpu core activationLiam1-172/+49
2023-11-25arm: Implement native code execution backendLiam1-0/+3
2023-07-15Fixes and workarounds to make UBSan happier on macOScomex1-1/+1
There are still some other issues not addressed here, but it's a start. Workarounds for false-positive reports: - `RasterizerAccelerated`: Put a gigantic array behind a `unique_ptr`, because UBSan has a [hardcoded limit](https://stackoverflow.com/questions/64531383/c-runtime-error-using-fsanitize-undefined-object-has-a-possibly-invalid-vp) of how big it thinks objects can be, specifically when dealing with offset-to-top values used with multiple inheritance. Hopefully this doesn't have a performance impact. - `QueryCacheBase::QueryCacheBase`: Avoid an operation that UBSan thinks is UB even though it at least arguably isn't. See the link in the comment for more information. Fixes for correct reports: - `PageTable`, `Memory`: Use `uintptr_t` values instead of pointers to avoid UB from pointer overflow (when pointer arithmetic wraps around the address space). - `KScheduler::Reload`: `thread->GetOwnerProcess()` can be `nullptr`; avoid calling methods on it in this case. (The existing code returns a garbage reference to a field, which is then passed into `LoadWatchpointArray`, and apparently it's never used, so it's harmless in practice but still triggers UBSan.) - `KAutoObject::Close`: This function calls `this->Destroy()`, which overwrites the beginning of the object with junk (specifically a free list pointer). Then it calls `this->UnregisterWithKernel()`. UBSan complains about a type mismatch because the vtable has been overwritten, and I believe this is indeed UB. `UnregisterWithKernel` also loads `m_kernel` from the 'freed' object, which seems to be technically safe (the overwriting doesn't extend as far as that field), but seems dubious. Switch to a `static` method and load `m_kernel` in advance.
2023-06-13core: decouple ARM interface from DynarmicLiam1-15/+22
2023-03-22kernel: use KTypedAddress for addressesLiam1-4/+4
2023-02-07kernel/svc: switch to generated wrappersLiam1-0/+1
2022-07-27chore: make yuzu REUSE compliantAndrea Pappacoda1-3/+2
[REUSE] is a specification that aims at making file copyright information consistent, so that it can be both human and machine readable. It basically requires that all files have a header containing copyright and licensing information. When this isn't possible, like when dealing with binary assets, generated files or embedded third-party dependencies, it is permitted to insert copyright information in the `.reuse/dep5` file. Oh, and it also requires that all the licenses used in the project are present in the `LICENSES` folder, that's why the diff is so huge. This can be done automatically with `reuse download --all`. The `reuse` tool also contains a handy subcommand that analyzes the project and tells whether or not the project is (still) compliant, `reuse lint`. Following REUSE has a few advantages over the current approach: - Copyright information is easy to access for users / downstream - Files like `dist/license.md` do not need to exist anymore, as `.reuse/dep5` is used instead - `reuse lint` makes it easy to ensure that copyright information of files like binary assets / images is always accurate and up to date To add copyright information of files that didn't have it I looked up who committed what and when, for each file. As yuzu contributors do not have to sign a CLA or similar I couldn't assume that copyright ownership was of the "yuzu Emulator Project", so I used the name and/or email of the commit author instead. [REUSE]: https://reuse.software Follow-up to 01cf05bc75b1e47beb08937439f3ed9339e7b254
2022-07-25kernel: unlayer CPU interrupt handlingLiam1-6/+5
2022-07-15dynarmic: Abort watchpoints ASAPMerry1-1/+1
2022-06-22dynarmic: Stop ReadCode callbacks to unmapped addressesLiam1-0/+1
2022-06-16core/debugger: memory breakpoint supportLiam1-1/+12
2022-06-01core/debugger: Improved stepping mechanism and misc fixesLiam1-2/+12
2022-06-01core/debugger: Implement new GDB stub debuggerLiam1-3/+2
2022-04-24Remove unused PrepareReschedule functionMerry1-3/+0
2022-04-21core/arm: separate backtrace collectionLiam1-7/+11
2022-04-03dynarmic: Better interruptsmerry1-0/+3
2022-02-02general: Replace NonCopyable struct with equivalentsLioncash1-1/+5
2021-05-27core/arm_interface: Call SVC after end of dynarmic block.Markus Wick1-3/+0
So we can modify all of dynarmic states within SVC without ExceptionalExit. Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
2021-05-26core/arm: Drop ChangeProcessorID.Markus Wick1-2/+0
This code was used to switch the CPU ID on thread switches. However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant. This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
2021-01-11core: arm: arm_interface: Fix shadowing errors.bunnei1-3/+4
2020-11-29core: arm: Implement InvalidateCacheRange for CPU cache invalidation.bunnei1-6/+13
2020-11-29hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.bunnei1-0/+3
2020-10-21Revert "core: Fix clang build"bunnei1-4/+4
2020-10-18core: Fix clang buildLioncash1-4/+4
Recent changes to the build system that made more warnings be flagged as errors caused building via clang to break. Fixes #4795
2020-06-28Core/Common: Address Feedback.Fernando Sahmkow1-1/+1
2020-06-27SVC: Implement 32-bits wrappers and update Dynarmic.Fernando Sahmkow1-3/+2
2020-06-27SingleCore: Use Cycle Timing instead of Host Timing.Fernando Sahmkow1-2/+4
2020-06-27General: Move ARM_Interface into Threads.Fernando Sahmkow1-0/+2
2020-06-27Core: Refactor ARM Interface.Fernando Sahmkow1-3/+6
2020-06-27ARM/WaitTree: Better track the CallStack for each thread.Fernando Sahmkow1-0/+3
2020-06-27Scheduler: Remove arm_interface lock and a few corrections.Fernando Sahmkow1-10/+0
2020-06-27General: Add better safety for JIT use.Fernando Sahmkow1-0/+10
2020-06-27General: Recover Prometheus project from harddrive failure Fernando Sahmkow1-1/+4
This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host Timing, Reworks the Kernel's Scheduler, Introduce Idle State and Suspended State, Recreates the bootmanager, Initializes Multicore system.
2020-04-17arm_interface: Ensure ThreadContext is zero'd out.bunnei1-16/+16
2020-03-03core: Implement separate A32/A64 ARM interfaces.bunnei1-13/+19
2019-11-27core: Prepare various classes for memory read/write migrationLioncash1-1/+7
Amends a few interfaces to be able to handle the migration over to the new Memory class by passing the class by reference as a function parameter where necessary. Notably, within the filesystem services, this eliminates two ReadBlock() calls by using the helper functions of HLERequestContext to do that for us.
2019-07-11core/arm: Remove obsolete Unicorn memory mappingLioncash1-7/+0
This was initially necessary when AArch64 JIT emulation was in its infancy and all memory-related instructions weren't implemented. Given the JIT now has all of these facilities implemented, we can remove these functions from the CPU interface.
2019-05-25arm_interface: Expand backtrace generationZach Hilman1-0/+11
Returns results as a vector of entries for further processing. Logs addresses, offsets, and mangled name.
2019-04-12core/cpu_core_manager: Create threads separately from initialization.Lioncash1-2/+12
Our initialization process is a little wonky than one would expect when it comes to code flow. We initialize the CPU last, as opposed to hardware, where the CPU obviously needs to be first, otherwise nothing else would work, and we have code that adds checks to get around this. For example, in the page table setting code, we check to see if the system is turned on before we even notify the CPU instances of a page table switch. This results in dead code (at the moment), because the only time a page table switch will occur is when the system is *not* running, preventing the emulated CPU instances from being notified of a page table switch in a convenient manner (technically the code path could be taken, but we don't emulate the process creation svc handlers yet). This moves the threads creation into its own member function of the core manager and restores a little order (and predictability) to our initialization process. Previously, in the multi-threaded cases, we'd kick off several threads before even the main kernel process was created and ready to execute (gross!). Now the initialization process is like so: Initialization: 1. Timers 2. CPU 3. Kernel 4. Filesystem stuff (kind of gross, but can be amended trivially) 5. Applet stuff (ditto in terms of being kind of gross) 6. Main process (will be moved into the loading step in a following change) 7. Telemetry (this should be initialized last in the future). 8. Services (4 and 5 should ideally be alongside this). 9. GDB (gross. Uses namespace scope state. Needs to be refactored into a class or booted altogether). 10. Renderer 11. GPU (will also have its threads created in a separate step in a following change). Which... isn't *ideal* per-se, however getting rid of the wonky intertwining of CPU state initialization out of this mix gets rid of most of the footguns when it comes to our initialization process.
2018-12-31arm_interface: Make LogBacktrace() a const member functionLioncash1-1/+1
This function doesn't modify instance state, so it can be made const.
2018-12-29Moved log backtrace to arm_interface.cpp. Added printing of error code to fatalDavid Marcec1-17/+7
2018-12-19Moved backtrace to ArmInterfaceDavid Marcec1-1/+17
2018-12-03Moved backtrace to ArmInterfaceDavid Marcec1-0/+2
Added to both dynarmic and unicorn
2018-09-30arm_interface: Add missing fpsr/tpidr members to the ThreadContext structLioncash1-2/+8
Internally within the kernel, it also includes a member variable for the floating-point status register, and TPIDR, so we should do the same here to match it. While we're at it, also fix up the size of the struct and add a static assertion to ensure it always stays the correct size.
2018-09-21arm_interface: Replace kernel vm_manager include with a forward declarationLioncash1-1/+4
Avoids an unnecessary inclusion and also uncovers three places where indirect inclusions were relied upon, which allows us to also resolve those.
2018-09-18arm_interface: Remove ARM11-isms from the CPU interfaceLioncash1-22/+31
This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
2018-09-15Port #4182 from Citra: "Prefix all size_t with std::"fearlessTobi1-2/+2
2018-08-25core: Namespace all code in the arm subdirectory under the Core namespaceLioncash1-0/+4
Gets all of these types and interfaces out of the global namespace.
2018-07-21CPU: Save and restore the TPIDR_EL0 system register on every context switch.Subv1-0/+4
Note that there's currently a dynarmic bug preventing this register from being written.
2018-07-21arm_interface: Remove unused tls_address member of ThreadContextLioncash1-3/+0
Currently, the TLS address is set within the scheduler, making this member unused.
2018-07-16scheduler: Clear exclusive state when switching contextsMerryMage1-0/+2
2018-03-16arm_interface: Support unmapping previously mapped memory.bunnei1-1/+5
2018-02-25Implements citra-emu/citra#3184N00byKing1-26/+3
2018-01-16clang-formatMerryMage1-1/+2
2018-01-12arm_dynarmic: Implement coreMerryMage1-7/+5
2018-01-03arm: Remove SkyEye/Dyncom code that is ARMv6-only.bunnei1-30/+0
2017-09-30arm_interface: Set TLS address for dynarmic core.bunnei1-0/+7
2017-09-30arm: Use 64-bit addressing in a bunch of places.bunnei1-14/+14
2017-09-30Moved down_count to CoreTimingHuw Pascoe1-9/+0
2017-09-25ARM_Interface: Implement PageTableChangedMerryMage1-0/+3
2016-12-22ThreadContext: Move from "core" to "arm_interface".bunnei1-6/+13
2016-09-19Manually tweak source formatting and then re-run clang-formatYuri Kunde Schlesner1-2/+1
2016-09-18Sources: Run clang-format on everything.Emmanuel Gil Peyrot1-4/+3
2016-09-15arm: ResetContext shouldn't be part of ARM_Interface.bunnei1-9/+0
2016-08-27ARM: add ClearInstructionCache functionwwylele1-0/+3
2016-05-17Set fpscr for new threadsJannik Vogel1-0/+1
2015-12-06arm_interface: Make GetNumInstructions constLioncash1-1/+1
2015-12-06arm_interface: directly initialize class membersLioncash1-7/+2
2015-08-07arm_interface: Implement interface for retrieving VFP registersLioncash1-0/+28
2015-05-11fixup! Set the TLS address in the schedulerSubv1-2/+1
2015-05-11Core/Memory: Give every emulated thread it's own TLS area.Subv1-1/+2
The TLS area for thread T with id Ti is located at TLS_AREA_VADDR + (Ti - 1) * 0x200. This allows some games like Mario Kart 7 to continue further.
2015-05-07Common: Remove common.hYuri Kunde Schlesner1-1/+0
2015-04-06arm_interface: Support retrieval/storage to CP15 registersLioncash1-0/+15
2015-03-16arm_interface: Get rid of GetTicks.Lioncash1-6/+0
Removes a TODO.
2015-02-10Scheduler refactor Pt. 1Kevin Hartman1-0/+9
* Simplifies scheduling logic, specifically regarding thread status. It should be much clearer which statuses are valid for a thread at any given point in the system. * Removes dead code from thread.cpp. * Moves the implementation of resetting a ThreadContext to the corresponding core's implementation. Other changes: * Fixed comments in arm interfaces. * Updated comments in thread.cpp * Removed confusing, useless, functions like MakeReady() and ChangeStatus() from thread.cpp. * Removed stack_size from Thread. In the CTR kernel, the thread's stack would be allocated before thread creation.
2015-01-09Move ThreadContext to core/core.h and deal with the falloutYuri Kunde Schlesner1-3/+5
2015-01-07CoreTiming: Ported the CoreTiming namespace from PPSSPPSubv1-0/+2
Implemented the required calls to make it work. CoreTiming: Added a new logging class Core_Timing.
2014-12-26ARM: Add a mechanism for faking CPU time elapsed during HLE.bunnei1-0/+6
- Also a few cleanups.
2014-12-21License changepurpasmart961-1/+1
2014-11-19Remove trailing spaces in every file but the ones imported from SkyEye, AOSP or generatedEmmanuel Gil Peyrot1-3/+3
2014-11-14ARM_Interface: Make destructor virtualLioncash1-1/+1
Fixes some warnings on OSX.
2014-06-02arm: added option to prepare CPU core (while mid-instruction) for thread reschedulebunnei1-0/+3
2014-06-01Added 'this' reference to num_instructions field so it's properly updated,as before the method was affecting the local method parameter rather than the class fieldDisruption1-1/+1
2014-05-21ARM_Interpreter/ARM_Interface: Fixed member variable naming to be consistent with style guidebunnei1-5/+5
2014-05-21ARM_Interface: added SaveContext and LoadContext functions for HLE thread switchingbunnei1-1/+15
2014-05-17updated how we call ARM core to make things much fasterbunnei1-5/+16
2014-05-12added option to set CPSR register to arm_interfacebunnei1-0/+6
2014-04-28removed DISALLOW_COPY_AND_ASSIGN in favor of NonCopyable classbunnei1-2/+1
2014-04-11missed this file with commit 95e5436fbunnei1-1/+10
2014-04-09fixed licensing and updated code style naming for arm_interface/arm_interpreter frontend modulebunnei1-9/+11
2014-04-09fixed project includes to use new directory structurebunnei1-2/+2
2014-04-09got rid of 'src' folders in each sub-projectbunnei1-0/+0
2014-04-09fixed some license headers that I missedbunnei1-23/+3
2014-04-05changed hw_lcd to use ARM core correct tick counter instead of [what was actually] just an instruction count. this seems to fix timing issues with the 3DS_Homebrew_Pong3Dv2 demo.bunnei1-5/+38
2014-04-05added a tick counterbunnei1-4/+12
2014-04-05- added an interface layer for ARM coresbunnei1-13/+25
- cleaned up core.cpp a bit
2013-09-26renamed from citrus to citraShizZy1-7/+7
2013-09-14renamed project to 'citrus'ShizZy1-8/+8
2013-09-06added core and mem_map files to the projectShizZy1-12/+12
2013-08-30adding initial project layoutShizZy1-0/+35