summaryrefslogtreecommitdiffstats
path: root/src/core/arm/dynarmic/arm_dynarmic_32.cpp (unfollow)
Commit message (Collapse)AuthorFilesLines
2023-12-26core: track separate heap allocation for linuxLiam1-0/+5
2023-12-23kernel: instantiate memory separately for each guest processLiam1-3/+3
2023-12-05arm: fix context save of vector regsLiam1-6/+4
2023-12-04core: refactor emulated cpu core activationLiam1-172/+155
2023-07-22core: remove remaining uses of dynamic_castLiam1-3/+3
2023-07-21settings,general: Rename non-confirming enumslat9nq1-3/+3
2023-06-28arm_dynarmic_32: Remove disabling of block linking on arm64Merry1-5/+0
2023-06-13core: decouple ARM interface from DynarmicLiam1-49/+15
2023-04-02core: arm_dynarmic_32: Update SaveContext/LoadContext.bunnei1-13/+10
2023-03-24memory: rename global memory references to application memoryLiam1-3/+3
2023-03-22kernel: use KTypedAddress for addressesLiam1-3/+3
2023-01-06externals: update dynarmic, xbyakLiam1-0/+4
2022-12-02core: add option to break on unmapped accessLiam1-2/+19
2022-11-09Initial ARM64 supportLiam1-0/+5
2022-10-27arm_interface: curb infinite recursion in stacktrace generationLiam1-1/+1
2022-08-20code: dodge PAGE_SIZE #defineKyle Kienapfel1-2/+2
Some header files, specifically for OSX and Musl libc define PAGE_SIZE to be a number This is great except in yuzu we're using PAGE_SIZE as a variable Specific example `static constexpr u64 PAGE_SIZE = u64(1) << PAGE_BITS;` PAGE_SIZE PAGE_BITS PAGE_MASK are all similar variables. Simply deleted the underscores, and then added YUZU_ prefix Might be worth noting that there are multiple uses in different classes/namespaces This list may not be exhaustive Core::Memory 12 bits (4096) QueryCacheBase 12 bits ShaderCache 14 bits (16384) TextureCache 20 bits (1048576, or 1MB) Fixes #8779
2022-08-09arm_dynarmic: Fix nullptr fastmem arenasMerry1-6/+9
Unable to enable fastmem of exclusive access without a valid fastmem arena.
2022-08-08core/arm: fix build errorLiam1-1/+5
2022-07-25kernel: unlayer CPU interrupt handlingLiam1-6/+7
2022-07-16core/arm: skip watchpoint checks when reading instructionsLiam1-3/+3
2022-07-15dynarmic: Abort watchpoints ASAPMerry1-3/+1
2022-06-25core/arm: better support for backtrace generationLiam1-5/+25
2022-06-22core/arm: increase minimum_run_cyclesLiam1-1/+1
2022-06-22core/arm: re-enable cycle countingmerry1-3/+10
2022-06-22dynarmic: Stop ReadCode callbacks to unmapped addressesLiam1-12/+30
2022-06-16core/debugger: memory breakpoint supportLiam1-11/+58
2022-06-01core/debugger: Improved stepping mechanism and misc fixesLiam1-34/+11
2022-06-01core/debugger: Implement new GDB stub debuggerLiam1-6/+29
2022-04-24Remove unused PrepareReschedule functionMerry1-4/+0
2022-04-23general: Convert source file copyright comments over to SPDXMorph1-3/+2
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
2022-04-21core/arm: separate backtrace collectionLiam1-0/+19
2022-04-13dynarmic: Fix single core modemerry1-1/+1
Regression introduced in a5d040df3d. Closes #8201.
2022-04-10dynarmic: Fix race when switching page tablesmerry1-20/+28
2022-04-05dynarmic: Print stack trace on unrecognised instruction or other exceptionmerry1-0/+2
2022-04-03arm_dynarmic: Use HaltReason for svc calls and reschedulesmerry1-10/+9
2022-04-03dynarmic: Better interruptsmerry1-11/+11
2022-03-26configuration: Add Paranoid CPU accuracy levelmerry1-22/+28
Disables most optimizations for the paranoid.
2022-03-23Revert "dynarmic: Reduce size of code caches"bunnei1-2/+2
2022-03-13dynarmic: Reduce size of code cachesMerry1-2/+2
2022-02-27dynarmic: Inline exclusive memory accessesmerry1-0/+12
Inlines implementation of exclusive instructions into JITted code, improving performance of applications relying heavily on these instructions. We also fastmem these instructions for additional speed, with support for appropriate recompilation on fastmem failure. An unsafe optimization to disable the intercore global_monitor is also provided, should one wish to rely solely on cmpxchg semantics for safety. See also: merryhime/dynarmic#664
2021-07-08settings, arm_dynarmic, yuzu qt: Move CPU debugging optionlat9nq1-1/+1
Decouples the CPU debugging mode from the enumeration to its own boolean. After this, it moves the CPU Debugging tab over to a sub tab underneath the Debug tab in the configuration UI.
2021-07-08arm_dynarmic{32,64}: Fixes from test buildlat9nq1-9/+3
Now sets optimizations regardless of the Settings. Drops unsafe fastmem optimization.
2021-07-08core,common,yuzu qt: Add CPU accuracy option 'Auto'lat9nq1-4/+18
The current CPU accuracy settings in yuzu are fairly polarized and require more than common knowledge to know what the optimal settings for yuzu would be. This adds a curated option called 'Auto' that applies a few at the moment known-good unsafe optimizations to Dynarmic.
2021-06-24common: Replace common_sizes into user-literalsWunkolo1-2/+5
Removes common_sizes.h in favor of having `_KiB`, `_MiB`, `_GiB`, etc user-literals within literals.h. To keep the global namespace clean, users will have to use: ``` using namespace Common::Literals; ``` to access these literals.
2021-06-20Update dynarmic and add new unsafe CPU option.Fernando Sahmkow1-0/+3
2021-06-11General: Add settings for fastmem and disabling adress space check.FernandoS271-1/+4
2021-06-11core: Make use of fastmemMarkus Wick1-0/+1
2021-05-29core/arm_interface: Improve the performance of memory fallbacks.Markus Wick1-13/+15
We just create one memory subsystem. This is a constant all the time. So there is no need to call the non-inlined parent.Memory() helper on every callback.
2021-05-29externals: Update dynarmic.Markus Wick1-3/+3
The new version supports fastmem on a64.
2021-05-27core/arm_interface: Call SVC after end of dynarmic block.Markus Wick1-6/+15
So we can modify all of dynarmic states within SVC without ExceptionalExit. Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
2021-05-26core/arm: Drop ChangeProcessorID.Markus Wick1-4/+0
This code was used to switch the CPU ID on thread switches. However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant. This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
2021-05-16core: Make variable shadowing a compile-time errorLioncash1-1/+1
Now that we have most of core free of shadowing, we can enable the warning as an error to catch anything that may be remaining and also eliminate this class of logic bug entirely.
2021-05-16general: Make CPU accuracy and related a Settings::Settinglat9nq1-5/+5
Required to make CPU accuracy and unsafe settings available to use as a per-game setting.
2021-05-04service: Resolve cases of member field shadowingLioncash1-6/+6
Now all that remains is for kernel code to be 'shadow-free' and then -Wshadow can be turned into an error.
2021-04-15common: Move settings to common from core.bunnei1-1/+1
- Removes a dependency on core and input_common from common.
2021-04-02arm_dynarmic: Increase size of code cacheMerryMage1-0/+4
2021-03-24arm_dynarmic: Always have a 'valid' jit instanceMerryMage1-23/+8
2021-03-21core: arm_dynarmic: Ensure JIT state is saved/restored on page table changes.bunnei1-0/+5
- We re-create the JIT here without preserving any state.
2021-02-01arm_dynarmic_32: Print out CPSR.T on exceptionMerryMage1-2/+3
2021-01-29arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext.bunnei1-0/+6
2021-01-29core: arm: Remove unnecessary JIT checks.bunnei1-12/+0
2021-01-29arm: arm_dynarmic: Skip calls when JIT is invalid.bunnei1-0/+12
- This can happen if called from an idle or suspension thread.
2021-01-09core: Silence unhandled enum in switch warningsReinUsesLisp1-8/+1
2021-01-02dynarmic: Add Unsafe_InaccurateNaN optimizationMerryMage1-0/+3
2020-12-30core/memory: Read and write page table atomicallyReinUsesLisp1-0/+1
Squash attributes into the pointer's integer, making them an uintptr_t pair containing 2 bits at the bottom and then the pointer. These bits are currently unused thanks to alignment requirements. Configure Dynarmic to mask out these bits on pointer reads. While we are at it, remove some unused attributes carried over from Citra. Read/Write and other hot functions use a two step unpacking process that is less readable to stop MSVC from emitting an extra AND instruction in the hot path: mov rdi,rcx shr rdx,0Ch mov r8,qword ptr [rax+8] mov rax,qword ptr [r8+rdx*8] mov rdx,rax -and al,3 and rdx,0FFFFFFFFFFFFFFFCh je Core::Memory::Memory::Impl::Read<unsigned char> mov rax,qword ptr [vaddr] movzx eax,byte ptr [rdx+rax]
2020-12-06hle: kernel: physical_core: Clear exclusive state after each run.bunnei1-0/+3
- This is closer to pre-multicore behavior, and works a bit better.
2020-11-29core: arm: Implement InvalidateCacheRange for CPU cache invalidation.bunnei1-0/+7
2020-11-29hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.bunnei1-0/+4
2020-11-04core: Remove usage of unicornLioncash1-0/+1
Unicorn long-since lost most of its use, due to dynarmic gaining support for handling most instructions. At this point any further issues encountered should be used to make dynarmic better. This also allows us to remove our dependency on Python.
2020-10-21Revert "core: Fix clang build"bunnei1-5/+5
2020-10-18core: Fix clang buildLioncash1-5/+5
Recent changes to the build system that made more warnings be flagged as errors caused building via clang to break. Fixes #4795
2020-08-16dynarmic: Add unsafe optimizationsMerryMage1-1/+12
2020-07-11configure_cpu: Show/Hide debugging optionsMerryMage1-23/+25
2020-07-11configuration: Add settings to enable/disable specific CPU optimizationsMerryMage1-4/+24
2020-06-28Core/Common: Address Feedback.Fernando Sahmkow1-2/+3
2020-06-27SVC: Implement 32-bits wrappers and update Dynarmic.Fernando Sahmkow1-1/+7
2020-06-27ARM: Update Dynarmic and Setup A32 according to latest interface.Fernando Sahmkow1-2/+39
2020-06-27ARMDynarmicInterface: Correct GCC Build Errors.Fernando Sahmkow1-3/+3
2020-06-27Dynarmic Interface: don't clear cache if JIT has not been created.Fernando Sahmkow1-0/+3
2020-06-27General: Cleanup legacy code.Fernando Sahmkow1-1/+0
2020-06-27SingleCore: Use Cycle Timing instead of Host Timing.Fernando Sahmkow1-12/+25
2020-06-27General: Move ARM_Interface into Threads.Fernando Sahmkow1-0/+4
2020-06-27Core: Refactor ARM Interface.Fernando Sahmkow1-3/+3
2020-06-27SVC/ARM: Correct svcSendSyncRequest and cache ticks on arm interface.Fernando Sahmkow1-2/+9
2020-06-27General: Fix microprofile on dynarmic/svc, fix wait tree showing which threads were running.Fernando Sahmkow1-4/+0
2020-06-27Core: Correct rebase.Fernando Sahmkow1-12/+6
2020-06-27General: Recover Prometheus project from harddrive failure Fernando Sahmkow1-3/+3
This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host Timing, Reworks the Kernel's Scheduler, Introduce Idle State and Suspended State, Recreates the bootmanager, Initializes Multicore system.
2020-06-22arm_dynarmic_32: Log under Core_ARM instead of HW_GPUMorph1-1/+1
2020-06-18arm_dynarmic_32: Fix implicit conversion error in SetTPIDR_EL0ReinUsesLisp1-1/+1
On MSVC builds we treat conversion warnings as errors.
2020-06-17arm_dynarmic_cp15: Update CP15MerryMage1-9/+7
2020-06-17arm_dynarmic_32: InterpreterFallback should never happenMerryMage1-2/+3
2020-04-17core: kernel: Move SVC to its own namesapce.bunnei1-1/+1
2020-03-03core: Implement separate A32/A64 ARM interfaces.bunnei1-0/+208