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path: root/src/core/arm/dynarmic/arm_dynarmic_32.cpp (follow)
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* dynarmic: Reduce size of code cachesMerry2022-03-131-2/+2
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* dynarmic: Inline exclusive memory accessesmerry2022-02-271-0/+12
| | | | | | | | | | | | | | | Inlines implementation of exclusive instructions into JITted code, improving performance of applications relying heavily on these instructions. We also fastmem these instructions for additional speed, with support for appropriate recompilation on fastmem failure. An unsafe optimization to disable the intercore global_monitor is also provided, should one wish to rely solely on cmpxchg semantics for safety. See also: merryhime/dynarmic#664
* settings, arm_dynarmic, yuzu qt: Move CPU debugging optionlat9nq2021-07-081-1/+1
| | | | | | Decouples the CPU debugging mode from the enumeration to its own boolean. After this, it moves the CPU Debugging tab over to a sub tab underneath the Debug tab in the configuration UI.
* arm_dynarmic{32,64}: Fixes from test buildlat9nq2021-07-081-9/+3
| | | | | Now sets optimizations regardless of the Settings. Drops unsafe fastmem optimization.
* core,common,yuzu qt: Add CPU accuracy option 'Auto'lat9nq2021-07-081-4/+18
| | | | | | | The current CPU accuracy settings in yuzu are fairly polarized and require more than common knowledge to know what the optimal settings for yuzu would be. This adds a curated option called 'Auto' that applies a few at the moment known-good unsafe optimizations to Dynarmic.
* common: Replace common_sizes into user-literalsWunkolo2021-06-241-2/+5
| | | | | | | | | | | | | Removes common_sizes.h in favor of having `_KiB`, `_MiB`, `_GiB`, etc user-literals within literals.h. To keep the global namespace clean, users will have to use: ``` using namespace Common::Literals; ``` to access these literals.
* Update dynarmic and add new unsafe CPU option.Fernando Sahmkow2021-06-201-0/+3
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* General: Add settings for fastmem and disabling adress space check.FernandoS272021-06-111-1/+4
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* core: Make use of fastmemMarkus Wick2021-06-111-0/+1
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* Merge pull request #6385 from degasus/save_memory_accessbunnei2021-05-311-13/+15
|\ | | | | core/memory: Check our memory fallbacks for out-of-bound behavior.
| * core/arm_interface: Improve the performance of memory fallbacks.Markus Wick2021-05-291-13/+15
| | | | | | | | | | We just create one memory subsystem. This is a constant all the time. So there is no need to call the non-inlined parent.Memory() helper on every callback.
* | externals: Update dynarmic.Markus Wick2021-05-291-3/+3
|/ | | | The new version supports fastmem on a64.
* core/arm_interface: Call SVC after end of dynarmic block.Markus Wick2021-05-271-6/+15
| | | | | | So we can modify all of dynarmic states within SVC without ExceptionalExit. Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
* core/arm: Drop ChangeProcessorID.Markus Wick2021-05-261-4/+0
| | | | | | This code was used to switch the CPU ID on thread switches. However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant. This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
* Merge pull request #6321 from lat9nq/per-game-cpubunnei2021-05-211-5/+5
|\ | | | | configuration: Add CPU tab to game properties and slight per-game settings rework
| * general: Make CPU accuracy and related a Settings::Settinglat9nq2021-05-161-5/+5
| | | | | | | | | | Required to make CPU accuracy and unsafe settings available to use as a per-game setting.
* | core: Make variable shadowing a compile-time errorLioncash2021-05-161-1/+1
|/ | | | | | Now that we have most of core free of shadowing, we can enable the warning as an error to catch anything that may be remaining and also eliminate this class of logic bug entirely.
* service: Resolve cases of member field shadowingLioncash2021-05-041-6/+6
| | | | | Now all that remains is for kernel code to be 'shadow-free' and then -Wshadow can be turned into an error.
* common: Move settings to common from core.bunnei2021-04-151-1/+1
| | | | - Removes a dependency on core and input_common from common.
* arm_dynarmic: Increase size of code cacheMerryMage2021-04-021-0/+4
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* arm_dynarmic: Always have a 'valid' jit instanceMerryMage2021-03-241-23/+8
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* core: arm_dynarmic: Ensure JIT state is saved/restored on page table changes.bunnei2021-03-211-0/+5
| | | | - We re-create the JIT here without preserving any state.
* arm_dynarmic_32: Print out CPSR.T on exceptionMerryMage2021-02-011-2/+3
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* arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext.bunnei2021-01-291-0/+6
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* core: arm: Remove unnecessary JIT checks.bunnei2021-01-291-12/+0
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* arm: arm_dynarmic: Skip calls when JIT is invalid.bunnei2021-01-291-0/+12
| | | | - This can happen if called from an idle or suspension thread.
* core: Silence unhandled enum in switch warningsReinUsesLisp2021-01-091-8/+1
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* dynarmic: Add Unsafe_InaccurateNaN optimizationMerryMage2021-01-021-0/+3
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* core/memory: Read and write page table atomicallyReinUsesLisp2020-12-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Squash attributes into the pointer's integer, making them an uintptr_t pair containing 2 bits at the bottom and then the pointer. These bits are currently unused thanks to alignment requirements. Configure Dynarmic to mask out these bits on pointer reads. While we are at it, remove some unused attributes carried over from Citra. Read/Write and other hot functions use a two step unpacking process that is less readable to stop MSVC from emitting an extra AND instruction in the hot path: mov rdi,rcx shr rdx,0Ch mov r8,qword ptr [rax+8] mov rax,qword ptr [r8+rdx*8] mov rdx,rax -and al,3 and rdx,0FFFFFFFFFFFFFFFCh je Core::Memory::Memory::Impl::Read<unsigned char> mov rax,qword ptr [vaddr] movzx eax,byte ptr [rdx+rax]
* hle: kernel: physical_core: Clear exclusive state after each run.bunnei2020-12-061-0/+3
| | | | - This is closer to pre-multicore behavior, and works a bit better.
* core: arm: Implement InvalidateCacheRange for CPU cache invalidation.bunnei2020-11-291-0/+7
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* hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.bunnei2020-11-291-0/+4
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* core: Remove usage of unicornLioncash2020-11-041-0/+1
| | | | | | | | Unicorn long-since lost most of its use, due to dynarmic gaining support for handling most instructions. At this point any further issues encountered should be used to make dynarmic better. This also allows us to remove our dependency on Python.
* Revert "core: Fix clang build"bunnei2020-10-211-5/+5
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* core: Fix clang buildLioncash2020-10-181-5/+5
| | | | | | | Recent changes to the build system that made more warnings be flagged as errors caused building via clang to break. Fixes #4795
* dynarmic: Add unsafe optimizationsMerryMage2020-08-161-1/+12
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* configure_cpu: Show/Hide debugging optionsMerryMage2020-07-111-23/+25
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* configuration: Add settings to enable/disable specific CPU optimizationsMerryMage2020-07-111-4/+24
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* Core/Common: Address Feedback.Fernando Sahmkow2020-06-281-2/+3
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* SVC: Implement 32-bits wrappers and update Dynarmic.Fernando Sahmkow2020-06-271-1/+7
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* ARM: Update Dynarmic and Setup A32 according to latest interface.Fernando Sahmkow2020-06-271-2/+39
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* ARMDynarmicInterface: Correct GCC Build Errors.Fernando Sahmkow2020-06-271-3/+3
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* Dynarmic Interface: don't clear cache if JIT has not been created.Fernando Sahmkow2020-06-271-0/+3
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* General: Cleanup legacy code.Fernando Sahmkow2020-06-271-1/+0
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* SingleCore: Use Cycle Timing instead of Host Timing.Fernando Sahmkow2020-06-271-12/+25
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* General: Move ARM_Interface into Threads.Fernando Sahmkow2020-06-271-0/+4
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* Core: Refactor ARM Interface.Fernando Sahmkow2020-06-271-3/+3
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* SVC/ARM: Correct svcSendSyncRequest and cache ticks on arm interface.Fernando Sahmkow2020-06-271-2/+9
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* General: Fix microprofile on dynarmic/svc, fix wait tree showing which threads were running.Fernando Sahmkow2020-06-271-4/+0
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* Core: Correct rebase.Fernando Sahmkow2020-06-271-12/+6
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* General: Recover Prometheus project from harddrive failure Fernando Sahmkow2020-06-271-3/+3
| | | | | | | This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host Timing, Reworks the Kernel's Scheduler, Introduce Idle State and Suspended State, Recreates the bootmanager, Initializes Multicore system.
* arm_dynarmic_32: Log under Core_ARM instead of HW_GPUMorph2020-06-221-1/+1
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* arm_dynarmic_32: Fix implicit conversion error in SetTPIDR_EL0ReinUsesLisp2020-06-181-1/+1
| | | | On MSVC builds we treat conversion warnings as errors.
* arm_dynarmic_cp15: Update CP15MerryMage2020-06-171-9/+7
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* arm_dynarmic_32: InterpreterFallback should never happenMerryMage2020-06-171-2/+3
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* core: kernel: Move SVC to its own namesapce.bunnei2020-04-171-1/+1
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* core: Implement separate A32/A64 ARM interfaces.bunnei2020-03-031-0/+208
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