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* dynarmic: Reduce size of code cachesMerry2022-03-131-2/+2
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* dynarmic: Inline exclusive memory accessesmerry2022-02-271-0/+13
| | | | | | | | | | | | | | | Inlines implementation of exclusive instructions into JITted code, improving performance of applications relying heavily on these instructions. We also fastmem these instructions for additional speed, with support for appropriate recompilation on fastmem failure. An unsafe optimization to disable the intercore global_monitor is also provided, should one wish to rely solely on cmpxchg semantics for safety. See also: merryhime/dynarmic#664
* arm: dynarmic: Cleanup icache op handlingjam1garner2021-11-221-10/+9
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* arm: dynarmic: Implement icache op handling for 'ic iallu' instructionjam1garner2021-11-221-0/+3
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* arm: dynarmic: Implement icache op handling for 'ic ivau' instructionjam1garner2021-11-221-0/+18
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* core: Remove unused includesameerj2021-11-041-1/+0
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* Fixed ARM_Dynamic_64 StepAndrew Strelsky2021-10-241-1/+1
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* settings, arm_dynarmic, yuzu qt: Move CPU debugging optionlat9nq2021-07-081-1/+1
| | | | | | Decouples the CPU debugging mode from the enumeration to its own boolean. After this, it moves the CPU Debugging tab over to a sub tab underneath the Debug tab in the configuration UI.
* arm_dynarmic_64: Re-add fastmem_address_space_bits to Auto settinglat9nq2021-07-081-0/+1
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* arm_dynarmic{32,64}: Fixes from test buildlat9nq2021-07-081-9/+2
| | | | | Now sets optimizations regardless of the Settings. Drops unsafe fastmem optimization.
* core,common,yuzu qt: Add CPU accuracy option 'Auto'lat9nq2021-07-081-4/+18
| | | | | | | The current CPU accuracy settings in yuzu are fairly polarized and require more than common knowledge to know what the optimal settings for yuzu would be. This adds a curated option called 'Auto' that applies a few at the moment known-good unsafe optimizations to Dynarmic.
* common: Replace common_sizes into user-literalsWunkolo2021-06-241-2/+4
| | | | | | | | | | | | | Removes common_sizes.h in favor of having `_KiB`, `_MiB`, `_GiB`, etc user-literals within literals.h. To keep the global namespace clean, users will have to use: ``` using namespace Common::Literals; ``` to access these literals.
* General: Add settings for fastmem and disabling adress space check.FernandoS272021-06-111-1/+7
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* core: Make use of fastmemMarkus Wick2021-06-111-0/+4
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* Merge pull request #6385 from degasus/save_memory_accessbunnei2021-05-311-16/+16
|\ | | | | core/memory: Check our memory fallbacks for out-of-bound behavior.
| * core/arm_interface: Improve the performance of memory fallbacks.Markus Wick2021-05-291-16/+16
| | | | | | | | | | We just create one memory subsystem. This is a constant all the time. So there is no need to call the non-inlined parent.Memory() helper on every callback.
* | externals: Update dynarmic.Markus Wick2021-05-291-2/+2
|/ | | | The new version supports fastmem on a64.
* core/arm_interface: Call SVC after end of dynarmic block.Markus Wick2021-05-271-6/+15
| | | | | | So we can modify all of dynarmic states within SVC without ExceptionalExit. Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
* core/arm: Drop ChangeProcessorID.Markus Wick2021-05-261-4/+0
| | | | | | This code was used to switch the CPU ID on thread switches. However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant. This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
* Merge pull request #6321 from lat9nq/per-game-cpubunnei2021-05-211-5/+5
|\ | | | | configuration: Add CPU tab to game properties and slight per-game settings rework
| * general: Make CPU accuracy and related a Settings::Settinglat9nq2021-05-161-5/+5
| | | | | | | | | | Required to make CPU accuracy and unsafe settings available to use as a per-game setting.
* | core: Make variable shadowing a compile-time errorLioncash2021-05-161-1/+1
|/ | | | | | Now that we have most of core free of shadowing, we can enable the warning as an error to catch anything that may be remaining and also eliminate this class of logic bug entirely.
* hle: kernel: Rename Process to KProcess.bunnei2021-05-061-1/+1
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* service: Resolve cases of member field shadowingLioncash2021-05-041-6/+6
| | | | | Now all that remains is for kernel code to be 'shadow-free' and then -Wshadow can be turned into an error.
* common: Move settings to common from core.bunnei2021-04-151-1/+1
| | | | - Removes a dependency on core and input_common from common.
* arm_dynarmic: Increase size of code cacheMerryMage2021-04-021-0/+4
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* arm_dynarmic: Always have a 'valid' jit instanceMerryMage2021-03-241-25/+13
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* core: arm_dynarmic: Ensure JIT state is saved/restored on page table changes.bunnei2021-03-211-0/+5
| | | | - We re-create the JIT here without preserving any state.
* arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext.bunnei2021-01-291-0/+6
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* core: arm: Remove unnecessary JIT checks.bunnei2021-01-291-12/+0
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* arm: arm_dynarmic: Skip calls when JIT is invalid.bunnei2021-01-291-0/+12
| | | | - This can happen if called from an idle or suspension thread.
* dynarmic: Add Unsafe_InaccurateNaN optimizationMerryMage2021-01-021-0/+3
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* core/memory: Read and write page table atomicallyReinUsesLisp2020-12-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Squash attributes into the pointer's integer, making them an uintptr_t pair containing 2 bits at the bottom and then the pointer. These bits are currently unused thanks to alignment requirements. Configure Dynarmic to mask out these bits on pointer reads. While we are at it, remove some unused attributes carried over from Citra. Read/Write and other hot functions use a two step unpacking process that is less readable to stop MSVC from emitting an extra AND instruction in the hot path: mov rdi,rcx shr rdx,0Ch mov r8,qword ptr [rax+8] mov rax,qword ptr [r8+rdx*8] mov rdx,rax -and al,3 and rdx,0FFFFFFFFFFFFFFFCh je Core::Memory::Memory::Impl::Read<unsigned char> mov rax,qword ptr [vaddr] movzx eax,byte ptr [rdx+rax]
* hle: kernel: Rewrite scheduler implementation based on Mesopshere.bunnei2020-12-061-1/+1
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* hle: kernel: physical_core: Clear exclusive state after each run.bunnei2020-12-061-0/+3
| | | | - This is closer to pre-multicore behavior, and works a bit better.
* core: arm: Implement InvalidateCacheRange for CPU cache invalidation.bunnei2020-11-291-0/+7
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* hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.bunnei2020-11-291-0/+4
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* core: Eliminate remaining usages of the global system instanceLioncash2020-11-271-11/+0
| | | | | | Removes all remaining usages of the global system instance. After this, migration can begin to migrate to being constructed and managed entirely by the various frontends.
* core: Remove usage of unicornLioncash2020-11-041-21/+8
| | | | | | | | Unicorn long-since lost most of its use, due to dynarmic gaining support for handling most instructions. At this point any further issues encountered should be used to make dynarmic better. This also allows us to remove our dependency on Python.
* Revert "core: Fix clang build"bunnei2020-10-211-5/+5
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* core: Fix clang buildLioncash2020-10-181-5/+5
| | | | | | | Recent changes to the build system that made more warnings be flagged as errors caused building via clang to break. Fixes #4795
* dynarmic: Add unsafe optimizationsMerryMage2020-08-161-1/+12
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* configure_cpu: Show/Hide debugging optionsMerryMage2020-07-111-23/+25
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* configuration: Add settings to enable/disable specific CPU optimizationsMerryMage2020-07-111-6/+26
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* Core/Common: Address Feedback.Fernando Sahmkow2020-06-281-2/+3
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* ARM: Update Dynarmic and Setup A32 according to latest interface.Fernando Sahmkow2020-06-271-64/+1
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* ARMDynarmicInterface: Correct GCC Build Errors.Fernando Sahmkow2020-06-271-3/+3
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* ARMInterface/Externals: Update dynarmic and fit to latest version.Fernando Sahmkow2020-06-271-7/+7
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* ARMInterface: Correct rebase errors.Fernando Sahmkow2020-06-271-2/+2
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* Dynarmic Interface: don't clear cache if JIT has not been created.Fernando Sahmkow2020-06-271-0/+3
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* General: Cleanup legacy code.Fernando Sahmkow2020-06-271-1/+0
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* SingleCore: Use Cycle Timing instead of Host Timing.Fernando Sahmkow2020-06-271-13/+26
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* General: Move ARM_Interface into Threads.Fernando Sahmkow2020-06-271-0/+4
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* Core: Refactor ARM Interface.Fernando Sahmkow2020-06-271-5/+8
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* X64 Clock: Reduce accuracy to be less or equal to guest accuracy.Fernando Sahmkow2020-06-271-0/+3
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* SVC/ARM: Correct svcSendSyncRequest and cache ticks on arm interface.Fernando Sahmkow2020-06-271-2/+10
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* ARM: Addapt to new Exclusive Monitor Interface.Fernando Sahmkow2020-06-271-12/+10
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* General: Fix microprofile on dynarmic/svc, fix wait tree showing which threads were running.Fernando Sahmkow2020-06-271-4/+1
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* ARM/Memory: Correct Exclusive Monitor and Implement Exclusive Memory Writes.Fernando Sahmkow2020-06-271-13/+53
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* General: Recover Prometheus project from harddrive failure Fernando Sahmkow2020-06-271-17/+11
| | | | | | | This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host Timing, Reworks the Kernel's Scheduler, Introduce Idle State and Suspended State, Recreates the bootmanager, Initializes Multicore system.
* arm_dynarmic_64: Log the instruction when an exception is raisedMorph2020-06-221-2/+2
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* physical_core: Make use of std::make_unique instead of std::make_shared in ctorLioncash2020-04-241-4/+3
| | | | | | | We can also allow unicorn to be constructed in 32-bit mode or 64-bit mode to satisfy the need for both interpreter instances. Allows this code to compile successfully of non x86-64 architectures.
* dynarmic: Add option to disable CPU JIT optimizationsMerryMage2020-04-201-2/+8
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* dynarmic: Enable strict alignment checks.bunnei2020-04-171-1/+4
| | | | - Also add a missing include.
* core: kernel: Move SVC to its own namesapce.bunnei2020-04-171-1/+1
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* core: Implement separate A32/A64 ARM interfaces.bunnei2020-03-031-0/+320
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