summaryrefslogtreecommitdiffstats
path: root/src/core/arm/dynarmic (follow)
Commit message (Collapse)AuthorAgeFilesLines
* arm_interface: Remove ARM11-isms from the CPU interfaceLioncash2018-09-182-26/+15
| | | | | | | | | This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
* Port #4182 from Citra: "Prefix all size_t with std::"fearlessTobi2018-09-152-24/+25
|
* Update microprofile scopes.Markus Wick2018-09-041-0/+4
| | | | | | Blame the subsystems which deserve the blame :) The updated list is not complete, just the ones I've spotted on random sampling the stack trace.
* core/core: Replace includes with forward declarations where applicableLioncash2018-08-311-0/+1
| | | | | | | | | | | The follow-up to e2457418dae19b889b2ad85255bb95d4cd0e4bff, which replaces most of the includes in the core header with forward declarations. This makes it so that if any of the headers the core header was previously including change, then no one will need to rebuild the bulk of the core, due to core.h being quite a prevalent inclusion. This should make turnaround for changes much faster for developers.
* core: Namespace all code in the arm subdirectory under the Core namespaceLioncash2018-08-252-0/+8
| | | | Gets all of these types and interfaces out of the global namespace.
* dynarmic: Update to 550d662MerryMage2018-08-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | 550d662 load_store_exclusive: Define s == t state to be Constraint_NONE 0b69381 A64/translate: Allow for unpredictable behaviour to be defined 6d236d4 system: Implement MRS CNTFRQ_EL0 6cbb6fb A32/testenv: Add missing headers 6729328 externals: Update xbyak to v5.67 1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805 9a95802 externals: Document subtrees 714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 8cab459 A64: Implement UQADD/UQSUB's scalar variants 18a8151 ir: Add opcodes for unsigned saturating add and subtract a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo() 29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8> e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR 55190bd fuzz_with_unicorn: Split utility functions into fuzz_util 23b049d A32/translate/load_store: Correct detection of writeback 7ec9f15 A32/translate: Add TranslateSingleInstruction efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode 08d1d19 A32/decoders: Split instruction list into include file 2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn f672368 microinstruction: Improve assert messages 7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
* arm_dynarmic: Remove IsExecuting check from PrepareRescheduleMerryMage2018-08-131-3/+1
| | | | No longer required. HaltExecution is a no-op if it is not currently executing.
* CPU/Timing: Use an approximated amortized amount of ticks when advancing timing.Subv2018-08-131-1/+10
| | | | | | | | We divide the number of ticks to add by the number of cores (4) to obtain a more or less rough estimate of the actual number of ticks added. This assumes that all 4 cores are doing similar work. Previously we were adding ~4 times the number of ticks, thus making the games think that time was going way too fast. This lets us bypass certain hangs in some games like Breath of the Wild. We should modify our CoreTiming to support multiple cores (both running in a single thread, and in multiple host threads).
* Merge pull request #876 from lioncash/includebunnei2018-08-011-1/+1
|\ | | | | kernel: Remove unnecessary includes
| * kernel: Remove unnecessary includesLioncash2018-07-311-1/+1
| | | | | | | | | | Removes unnecessary direct dependencies in some headers and also gets rid of indirect dependencies that were being relied on to be included.
* | arm_dynarmic: Make SetTlsAddress() prototype and definition consistentLioncash2018-07-311-1/+1
| | | | | | | | Makes the definition use the same type aliases as in its prototype.
* | arm_dynarmic: Remove unnecessary qualifying of ThreadContextLioncash2018-07-311-3/+3
| | | | | | | | | | Given the ARM_Dynarmic class inherits from ARM_Interface, we don't need to qualify here.
* | arm_dynarmic: Correct initializer list orderLioncash2018-07-311-5/+3
|/ | | | | | | | | Amends the initializer list to be in the same order that each variable would be initialized in. We also do this to ensure we don't use a bogus uninitialized instance of the exclusive monitor within MakeJit() We can also remove the jit member from the initializer list as this is initialized by PageTableChanged()
* arm_dynarmic: Make MakeJit() a const member functionLioncash2018-07-242-3/+3
| | | | | This functions doesn't modify instance state, so it can be a made a const member function.
* exclusive_monitor: Use consistent type alias for u64Lioncash2018-07-242-14/+12
| | | | | Uses the same type aliases we use for virtual addresses, and converts one lingering usage of std::array<uint64_t, 2> to u128 for consistency.
* Implement exclusive monitorMerryMage2018-07-222-8/+89
|
* Merge pull request #750 from lioncash/ctxbunnei2018-07-211-2/+0
|\ | | | | arm_interface: Remove unused tls_address member of ThreadContext
| * arm_interface: Remove unused tls_address member of ThreadContextLioncash2018-07-211-2/+0
| | | | | | | | | | Currently, the TLS address is set within the scheduler, making this member unused.
* | CPU: Save and restore the TPIDR_EL0 system register on every context switch.Subv2018-07-212-0/+10
|/ | | | Note that there's currently a dynarmic bug preventing this register from being written.
* scheduler: Clear exclusive state when switching contextsMerryMage2018-07-162-0/+5
|
* Update clang formatJames Rowe2018-07-031-1/+1
|
* Rename logging macro back to LOG_*James Rowe2018-07-031-1/+1
|
* general: Make formatting of logged hex values more straightforwardLioncash2018-05-021-1/+1
| | | | | | This makes the formatting expectations more obvious (e.g. any zero padding specified is padding that's entirely dedicated to the value being printed, not any pretty-printing that also gets tacked on).
* general: Convert assertion macros over to be fmt-compatibleLioncash2018-04-271-1/+1
|
* core: Replace remaining old non-generic logger usages with fmt-capable equivalentsLioncash2018-04-261-2/+2
| | | | | | LOG_GENERIC usages will be amended in a follow-up to keep API changes separate from interface changes, as it will require removing a parameter from the relevant function in the VMManager class.
* arm_dynarmic: Fix timingMerryMage2018-03-241-7/+3
|
* Merge pull request #193 from N00byKing/3184_2_robotic_boogaloobunnei2018-03-192-8/+16
|\ | | | | Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
| * Implements citra-emu/citra#3184N00byKing2018-02-252-8/+16
| |
* | arm_interface: Support unmapping previously mapped memory.bunnei2018-03-162-1/+5
| |
* | core: Move process creation out of global state.bunnei2018-03-141-1/+2
| |
* | dynarmic: Update to 6b4c6b0MerryMage2018-02-211-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
* | arm_dynarmic: LOG_INFO on unicorn fallbackMerryMage2018-02-211-0/+4
|/
* arm_dynarmic: Support direct page table accessMerryMage2018-02-121-6/+14
|
* dynarmic: Update to 41ae12263MerryMage2018-02-092-31/+45
| | | | Changes: Primarily implementing more A64 instructions
* Fixes some cast warnings, partial port of citra #3064 (#106)River City Ransomware2018-01-201-3/+3
| | | | | | | | * Fixes some cast warnings, partially fixes citra #3064 * Converted casts to uint32_t to u32 * Ran clang-format
* Update dynarmic to bc73004MerryMage2018-01-131-12/+17
| | | | | | | | | | | | | | | | | | bc73004 a64_merge_interpret_blocks: Remove debug output 4e656ed tests/A64: Randomize PSTATE.<NZCV> fd9530b A64: Optimization: Merge interpret blocks 3c9eb04 testenv: Use format constants 324f3fc tests/A64: Unicorn interface fixes 98ecbe7 tests/A64: Fuzz against unicorn b1d38e7 tests/A64: Move TestEnvironment to own header 5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 edadeea A64 inferface: Use two argument static_assert 9ab1304 A64: Add ExceptionRaised IR instruction 6843eed Update readme 7438d07 A64/translate: Add TranslateSingleInstruction function
* yuzu: Update license text to be consistent across project.bunnei2018-01-132-2/+2
|
* arm_dynarmic: Implement coreMerryMage2018-01-122-44/+142
|
* arm_dynarmic: More cleanup.bunnei2018-01-041-6/+0
|
* arm_dynarmic: Gut interface until dynarmic is ready for general use.bunnei2018-01-042-142/+44
|
* arm: Remove SkyEye/Dyncom code that is ARMv6-only.bunnei2018-01-034-147/+6
|
* Merge remote-tracking branch 'upstream/master' into nxbunnei2017-10-102-62/+48
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # Conflicts: # src/core/CMakeLists.txt # src/core/arm/dynarmic/arm_dynarmic.cpp # src/core/arm/dyncom/arm_dyncom.cpp # src/core/hle/kernel/process.cpp # src/core/hle/kernel/thread.cpp # src/core/hle/kernel/thread.h # src/core/hle/kernel/vm_manager.cpp # src/core/loader/3dsx.cpp # src/core/loader/elf.cpp # src/core/loader/ncch.cpp # src/core/memory.cpp # src/core/memory.h # src/core/memory_setup.h
| * Moved down_count to CoreTimingHuw Pascoe2017-09-302-10/+1
| |
| * ARM_Interface: Implement PageTableChangedMerryMage2017-09-252-6/+26
| |
| * Merge pull request #2842 from Subv/switchable_page_tableB3n302017-09-151-1/+3
| |\ | | | | | | Kernel/Memory: Give each process its own page table and allow switching the current page table upon reschedule
| | * CPU/Dynarmic: Disable the fast page-table access in dynarmic until it supports switching page tables at runtime.Subv2017-09-151-1/+3
| | |
| * | CPU/Dynarmic: Fixed a warning when incrementing the number of ticks in ExecuteInstructions.Subv2017-08-211-1/+1
| |/
* | arm_interface: Set TLS address for dynarmic core.bunnei2017-09-302-0/+16
| |
* | arm: Use 64-bit addressing in a bunch of places.bunnei2017-09-302-52/+85
|/
* arm_dynarmic: Update memory interfaceMerryMage2017-02-031-10/+10
|
* arm_dynarmic: CP15 supportMerryMage2017-02-034-5/+128
|
* Merge pull request #2366 from MerryMage/MemoryReadCodebunnei2016-12-221-0/+1
|\ | | | | arm_dynarmic: Provide MemoryReadCode callback
| * arm_dynarmic: Provide MemoryReadCode callbackMerryMage2016-12-221-0/+1
| | | | | | | | Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
* | ThreadContext: Move from "core" to "arm_interface".bunnei2016-12-222-8/+4
|/
* Core: Add a forgotten #include <cstring> for memcpy.Emmanuel Gil Peyrot2016-12-111-0/+1
|
* dynarmic: Add ticks based on ticks executed, not ticks requestedMerryMage2016-11-261-2/+2
|
* Expose page table to dynarmic for optimized reads and writes to the JITJames Rowe2016-11-251-0/+1
|
* Use negative priorities to avoid special-casing the self-includeYuri Kunde Schlesner2016-09-211-1/+1
|
* Remove empty newlines in #include blocks.Emmanuel Gil Peyrot2016-09-212-7/+2
| | | | | | | This makes clang-format useful on those. Also add a bunch of forgotten transitive includes, which otherwise prevented compilation.
* arm_dynarmic: Implement GetVFPSystemReg/SetVFPSystemReg.bunnei2016-09-151-5/+12
|
* arm: ResetContext shouldn't be part of ARM_Interface.bunnei2016-09-152-10/+0
|
* arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword.bunnei2016-09-151-1/+1
|
* dynarmic: Implement ARM CPU interface.bunnei2016-09-152-0/+227
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 10:04:27 +0100