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path: root/src/video_core/shader/shader_jit_x64.cpp (follow)
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* PICA: Fix MAD/MADI encodingJannik Vogel2016-03-151-27/+28
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* Add immediate mode vertex submissionDwayne Slater2016-03-031-0/+2
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* Merge pull request #1367 from yuriks/jit-jmpbunnei2016-01-271-5/+5
|\ | | | | Shader JIT: Fix off-by-one error when compiling JMPs
| * Shader JIT: Fix off-by-one error when compiling JMPsYuri Kunde Schlesner2016-01-241-5/+5
| | | | | | | | | | | | | | There was a mistake in the JMP code which meant that one instruction at the destination would be skipped when the jump was taken. This commit also changes the meaning of the culprit parameter to make it less confusing and avoid similar mistakes in the future.
* | Shader: Implement "invert condition" feature of IFU instructionYuri Kunde Schlesner2016-01-251-1/+3
|/ | | | | | If the bit 0 of the JMPU instruction is set, then the jump condition will be inverted. That is, a jump will happen when the boolean is false instead of when it is true.
* video_core: Remove unused variablesLioncash2015-09-101-1/+0
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* Shader JIT: Use SCALE constant from emitteraroulin2015-09-071-4/+4
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* Shader: Fix size_t to int casts of register offsetsaroulin2015-09-071-9/+15
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* Merge pull request #1088 from aroulin/x64-emitter-abi-callbunnei2015-09-021-26/+17
|\ | | | | x64: Proper stack alignment in shader JIT function calls
| * x64: Proper stack alignment in shader JIT function callsaroulin2015-09-011-26/+17
| | | | | | | | | | Import Dolphin stack handling and register saving routines Also removes the x86 parts from abi files
* | video_core: Fix format specifiers warningsaroulin2015-09-021-1/+2
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* Shader JIT: Fix SGE/SGEI NaN behavioraroulin2015-08-311-3/+3
| | | | | SGE was incorrectly emulated w.r.t. NaN behavior as the CMPSS SSE instruction was used with NLT
* Merge pull request #1065 from yuriks/shader-fpYuri Kunde Schlesner2015-08-281-54/+73
|\ | | | | Shader FP compliance fixes
| * Shader JIT: Tiny micro-optimization in DPHYuri Kunde Schlesner2015-08-241-4/+4
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| * Shaders: Fix multiplications between 0.0 and infYuri Kunde Schlesner2015-08-241-39/+39
| | | | | | | | | | | | | | | | The PICA200 semantics for multiplication are so that when multiplying inf by exactly 0.0, the result is 0.0, instead of NaN, as defined by IEEE. This is relied upon by games. Fixes #1024 (missing OoT interface items)
| * Shaders: Explicitly conform to PICA semantics in MAX/MINYuri Kunde Schlesner2015-08-241-0/+2
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| * Shader JIT: Add name to second scratch register (XMM4)Yuri Kunde Schlesner2015-08-241-3/+5
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| * Shader JIT: Fix CMP NaN behavior to match hardwareYuri Kunde Schlesner2015-08-241-8/+23
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* | Shader JIT: Fix float to integer rounding in MOVAaroulin2015-08-271-2/+2
| | | | | | | | MOVA converts new address register values from floats to integers using truncation
* | shader_jit: Replace two MDisp usages with MatRLioncash2015-08-241-2/+2
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* Merge pull request #1062 from aroulin/shader-rcp-rsqbunnei2015-08-231-4/+6
|\ | | | | Shader: RCP and RSQ computes only the 1st component
| * Shader: RCP and RSQ computes only the 1st componentaroulin2015-08-231-4/+6
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* | Shader: implement DPH/DPHI in JITaroulin2015-08-221-2/+35
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* Shader: implement SGE, SGEI and SLT in JITaroulin2015-08-191-14/+34
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* Shader: Save caller-saved registers in JIT before a CALLaroulin2015-08-191-0/+30
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* Shader: implement EX2 and LG2 in JITaroulin2015-08-171-2/+20
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* Introduce a shader tracer to allow inspection of input/output values for each processed instruction.Tony Wasserka2015-08-161-4/+4
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* Shader: Use a POD struct for registers.bunnei2015-08-161-6/+6
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* Common: Cleanup CPU capability detection code.bunnei2015-08-161-5/+5
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* Common: Move cpu_detect to x64 directory.bunnei2015-08-161-2/+1
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* x64: Refactor to remove fake interfaces and general cleanups.bunnei2015-08-161-6/+14
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* JIT: Support negative address offsets.bunnei2015-08-161-26/+25
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* Shader: Initial implementation of x86_x64 JIT compiler for Pica vertex shaders.bunnei2015-08-161-0/+669
- Config: Add an option for selecting to use shader JIT or interpreter. - Qt: Add a menu option for enabling/disabling the shader JIT.