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authorbunnei <bunneidev@gmail.com>2016-08-23 20:00:06 +0200
committerGitHub <noreply@github.com>2016-08-23 20:00:06 +0200
commit5b9e41bf1c891a36526a0d8844fb40bbc3b1e870 (patch)
treea591c269b37df61ba81873e72ea45bccd8bc8d37
parentcitra: Default to HW renderer. (diff)
parentdyncom: Read-after-write in SMLA (diff)
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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 6d5fb7aec..c8d45c6db 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -2820,10 +2820,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15);
else
operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
- RD = operand1 * operand2 + RN;
- if (AddOverflow(operand1 * operand2, RN, RD))
+ u32 product = operand1 * operand2;
+ u32 result = product + RN;
+ if (AddOverflow(product, RN, result))
cpu->Cpsr |= (1 << 27);
+ RD = result;
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(smla_inst));