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| author | David Marcec <dmarcecguzman@gmail.com> | 2018-09-01 11:05:10 +0200 |
|---|---|---|
| committer | David Marcec <dmarcecguzman@gmail.com> | 2018-09-01 11:05:10 +0200 |
| commit | 6f8ed9508dd1f7e104349bcf76acdf40da996e4c (patch) | |
| tree | 7dda05b50062ef7b5e8212dfc40168acecfae02c | |
| parent | Merge pull request #1196 from FearlessTobi/ccache-consistency (diff) | |
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| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 5 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 10 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 3e4efbe0c..f07992131 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -332,7 +332,12 @@ union Instruction { } ipa; union { + BitField<39, 2, u64> tab5cb8_2; + BitField<41, 3, u64> tab5c68_1; + BitField<44, 2, u64> tab5c68_0; + BitField<47, 1, u64> cc; BitField<48, 1, u64> negate_b; + BitField<50, 1, u64> saturate; } fmul; union { diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 391c92d47..f33e8d70f 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -1038,6 +1038,16 @@ private: case OpCode::Id::FMUL_R: case OpCode::Id::FMUL_IMM: { // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. + ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented", + instr.fmul.tab5cb8_2.Value()); + ASSERT_MSG(instr.fmul.tab5c68_1 == 0, "FMUL tab5cb8_1({}) is not implemented", + instr.fmul.tab5c68_1.Value()); + ASSERT_MSG(instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented", + instr.fmul.tab5c68_0 + .Value()); // SMO typical sends 1 here which seems to be the default + ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented"); + ASSERT_MSG(instr.fmul.saturate == 0, "FMUL saturate is not implemented"); + op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b); regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, instr.alu.saturate_d); |