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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-17 21:09:23 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:51 +0100
commit80183de8846ccf62631d48451535f9a6a4cb8284 (patch)
tree5638dffc94d78eb26fffbff72bdef4272b1f52d1
parentshader_decode: Implement ISET (diff)
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-rw-r--r--src/video_core/shader/decode/bfi.cpp23
1 files changed, 22 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/bfi.cpp b/src/video_core/shader/decode/bfi.cpp
index b94d46ce6..6a851b22e 100644
--- a/src/video_core/shader/decode/bfi.cpp
+++ b/src/video_core/shader/decode/bfi.cpp
@@ -16,7 +16,28 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
- UNIMPLEMENTED();
+ UNIMPLEMENTED_IF(instr.generates_cc);
+
+ const auto [base, packed_shift] = [&]() -> std::tuple<Node, Node> {
+ switch (opcode->get().GetId()) {
+ case OpCode::Id::BFI_IMM_R:
+ return {GetRegister(instr.gpr39), Immediate(instr.alu.GetSignedImm20_20())};
+ default:
+ UNREACHABLE();
+ }
+ }();
+ const Node insert = GetRegister(instr.gpr8);
+
+ const Node offset =
+ Operation(OperationCode::UBitwiseAnd, NO_PRECISE, packed_shift, Immediate(0xff));
+
+ Node bits =
+ Operation(OperationCode::ULogicalShiftRight, NO_PRECISE, packed_shift, Immediate(8));
+ bits = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, bits, Immediate(0xff));
+
+ const Node value =
+ Operation(OperationCode::UBitfieldInsert, PRECISE, base, insert, offset, bits);
+ SetRegister(bb, instr.gpr0, value);
return pc;
}