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author | Merry <git@mary.rs> | 2022-04-24 13:10:16 +0200 |
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committer | Merry <git@mary.rs> | 2022-04-24 13:10:16 +0200 |
commit | 91a6df0361708176fc5500d9783c5266e52eb7b7 (patch) | |
tree | 2baae9e2c1a57c8d26be9ed8d117958f69f3882f | |
parent | Merge pull request #8249 from german77/queued (diff) | |
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-rw-r--r-- | src/core/arm/arm_interface.h | 3 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.cpp | 4 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.h | 1 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 4 | ||||
-rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.h | 1 | ||||
-rw-r--r-- | src/core/core.cpp | 4 | ||||
-rw-r--r-- | src/core/core.h | 3 |
7 files changed, 0 insertions, 20 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h index bcec4b3b8..8ce973a77 100644 --- a/src/core/arm/arm_interface.h +++ b/src/core/arm/arm_interface.h @@ -174,9 +174,6 @@ public: /// Clears the exclusive monitor's state. virtual void ClearExclusiveState() = 0; - /// Prepare core for thread reschedule (if needed to correctly handle state) - virtual void PrepareReschedule() = 0; - /// Signal an interrupt and ask the core to halt as soon as possible. virtual void SignalInterrupt() = 0; diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp index 60e9edff2..781a77f6f 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp @@ -327,10 +327,6 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { jit.load()->LoadContext(context); } -void ARM_Dynarmic_32::PrepareReschedule() { - jit.load()->HaltExecution(break_loop); -} - void ARM_Dynarmic_32::SignalInterrupt() { jit.load()->HaltExecution(break_loop); } diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h index a25c9d277..abfe76644 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.h +++ b/src/core/arm/dynarmic/arm_dynarmic_32.h @@ -57,7 +57,6 @@ public: void LoadContext(const ThreadContext32& ctx) override; void LoadContext(const ThreadContext64& ctx) override {} - void PrepareReschedule() override; void SignalInterrupt() override; void ClearExclusiveState() override; diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index d8d3a38db..1b1334598 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp @@ -395,10 +395,6 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { SetTPIDR_EL0(ctx.tpidr); } -void ARM_Dynarmic_64::PrepareReschedule() { - jit.load()->HaltExecution(break_loop); -} - void ARM_Dynarmic_64::SignalInterrupt() { jit.load()->HaltExecution(break_loop); } diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h index 9680c7b99..01a7e4dad 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.h +++ b/src/core/arm/dynarmic/arm_dynarmic_64.h @@ -51,7 +51,6 @@ public: void LoadContext(const ThreadContext32& ctx) override {} void LoadContext(const ThreadContext64& ctx) override; - void PrepareReschedule() override; void SignalInterrupt() override; void ClearExclusiveState() override; diff --git a/src/core/core.cpp b/src/core/core.cpp index b5e2bcae2..8a887904d 100644 --- a/src/core/core.cpp +++ b/src/core/core.cpp @@ -505,10 +505,6 @@ bool System::IsPoweredOn() const { return impl->is_powered_on.load(std::memory_order::relaxed); } -void System::PrepareReschedule() { - // Deprecated, does nothing, kept for backward compatibility. -} - void System::PrepareReschedule(const u32 core_index) { impl->kernel.PrepareReschedule(core_index); } diff --git a/src/core/core.h b/src/core/core.h index 52ff90359..4a0c7dc84 100644 --- a/src/core/core.h +++ b/src/core/core.h @@ -194,9 +194,6 @@ public: [[nodiscard]] const Core::TelemetrySession& TelemetrySession() const; /// Prepare the core emulation for a reschedule - void PrepareReschedule(); - - /// Prepare the core emulation for a reschedule void PrepareReschedule(u32 core_index); /// Gets and resets core performance statistics |