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| author | bunnei <bunneidev@gmail.com> | 2018-06-16 04:04:03 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-16 04:04:03 +0200 |
| commit | fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a (patch) | |
| tree | 1ae606b3dceb2edee147e2199aabfe5f226e4a9d | |
| parent | Merge pull request #566 from bunnei/set_pos_w (diff) | |
| parent | gl_shader_decompiler: Implement LOP32I LogicOperation PassB. (diff) | |
| download | yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.tar yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.tar.gz yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.tar.bz2 yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.tar.lz yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.tar.xz yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.tar.zst yuzu-fb5bd0920db68eb65c1d57bcf5f10ca0d55e4a4a.zip | |
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 7ce150fda..9093eca32 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -930,20 +930,26 @@ private: if (instr.alu.lop.invert_b) imm = ~imm; + std::string op_b = std::to_string(imm); + switch (instr.alu.lop.operation) { case Tegra::Shader::LogicOperation::And: { - regs.SetRegisterToInteger(instr.gpr0, true, 0, - '(' + op_a + " & " + std::to_string(imm) + ')', 1, 1); + regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " & " + op_b + ')', + 1, 1); break; } case Tegra::Shader::LogicOperation::Or: { - regs.SetRegisterToInteger(instr.gpr0, true, 0, - '(' + op_a + " | " + std::to_string(imm) + ')', 1, 1); + regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " | " + op_b + ')', + 1, 1); break; } case Tegra::Shader::LogicOperation::Xor: { - regs.SetRegisterToInteger(instr.gpr0, true, 0, - '(' + op_a + " ^ " + std::to_string(imm) + ')', 1, 1); + regs.SetRegisterToInteger(instr.gpr0, true, 0, '(' + op_a + " ^ " + op_b + ')', + 1, 1); + break; + } + case Tegra::Shader::LogicOperation::PassB: { + regs.SetRegisterToInteger(instr.gpr0, true, 0, op_b, 1, 1); break; } default: |