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author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-05-19 21:32:38 +0200 |
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committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-23 03:51:32 +0200 |
commit | 96962c1d3c638d7cb15c89dcc9933b03237c03f6 (patch) | |
tree | afaea0e66a77b34b9aff49e27dae49a083783980 /src/shader_recompiler/backend | |
parent | glasm: Implement PREC on relevant instructions (diff) | |
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Diffstat (limited to 'src/shader_recompiler/backend')
-rw-r--r-- | src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp index f8a7e2781..066ed1012 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp @@ -29,7 +29,7 @@ void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value) } const Register phi_reg{ctx.reg_alloc.Consume(phi)}; const Value eval_value{ctx.reg_alloc.Consume(value)}; - switch (phi.InstRecursive()->Arg(0).Type()) { + switch (phi.Inst()->Flags<IR::Type>()) { case IR::Type::U1: case IR::Type::U32: case IR::Type::F32: |