6 files changed, 56 insertions, 1 deletions

diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 7aab163dc..6c6162cf3 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -8,6 +8,7 @@ namespace Tegra {
 namespace Engines {
 
 void Fermi2D::WriteReg(u32 method, u32 value) {}
+void Fermi2D::CallMethod(u32 method, const std::vector<u32>& parameters) {}
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 8967ddede..ce8920cee 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -4,6 +4,7 @@
 
 #pragma once
 
+#include <vector>
 #include "common/common_types.h"
 
 namespace Tegra {
@@ -16,6 +17,13 @@ public:
 
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
+
+    /**
+     * Handles a method call to this engine.
+     * @param method Method to call
+     * @param parameters Arguments to the method call
+     */
+    void CallMethod(u32 method, const std::vector<u32>& parameters);
 };
 
 } // namespace Engines
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 8c6d1172c..1b963e87e 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -8,8 +8,23 @@
 namespace Tegra {
 namespace Engines {
 
+const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
+    {0xE24, {"PrepareShader", 5, &Maxwell3D::PrepareShader}},
+};
+
 Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
 
+void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
+    auto itr = method_handlers.find(method);
+    if (itr == method_handlers.end()) {
+        LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
+        return;
+    }
+
+    ASSERT(itr->second.arguments == parameters.size());
+    (this->*itr->second.handler)(parameters);
+}
+
 void Maxwell3D::WriteReg(u32 method, u32 value) {
     ASSERT_MSG(method < Regs::NUM_REGS,
                "Invalid Maxwell3D register, increase the size of the Regs structure");
@@ -64,5 +79,7 @@ void Maxwell3D::DrawArrays() {
     LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
 }
 
+void Maxwell3D::PrepareShader(const std::vector<u32>& parameters) {}
+
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index a2ad28732..8870ef119 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -4,6 +4,8 @@
 
 #pragma once
 
+#include <unordered_map>
+#include <vector>
 #include "common/bit_field.h"
 #include "common/common_funcs.h"
 #include "common/common_types.h"
@@ -20,6 +22,13 @@ public:
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
 
+    /**
+     * Handles a method call to this engine.
+     * @param method Method to call
+     * @param parameters Arguments to the method call
+     */
+    void CallMethod(u32 method, const std::vector<u32>& parameters);
+
     /// Register structure of the Maxwell3D engine.
     /// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
     struct Regs {
@@ -112,13 +121,24 @@ public:
     static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
 
 private:
+    MemoryManager& memory_manager;
+
     /// Handles a write to the QUERY_GET register.
     void ProcessQueryGet();
 
     /// Handles a write to the VERTEX_END_GL register, triggering a draw.
     void DrawArrays();
 
-    MemoryManager& memory_manager;
+    /// Method call handlers
+    void PrepareShader(const std::vector<u32>& parameters);
+
+    struct MethodInfo {
+        const char* name;
+        u32 arguments;
+        void (Maxwell3D::*handler)(const std::vector<u32>& parameters);
+    };
+
+    static const std::unordered_map<u32, MethodInfo> method_handlers;
 };
 
 #define ASSERT_REG_POSITION(field_name, position)                                                  \
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index e4e5f9e5e..3bef7fe86 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -8,6 +8,7 @@ namespace Tegra {
 namespace Engines {
 
 void MaxwellCompute::WriteReg(u32 method, u32 value) {}
+void MaxwellCompute::CallMethod(u32 method, const std::vector<u32>& parameters) {}
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h
index 7262e1bcb..5fc7ed635 100644
--- a/src/video_core/engines/maxwell_compute.h
+++ b/src/video_core/engines/maxwell_compute.h
@@ -4,6 +4,7 @@
 
 #pragma once
 
+#include <vector>
 #include "common/common_types.h"
 
 namespace Tegra {
@@ -16,6 +17,13 @@ public:
 
     /// Write the value to the register identified by method.
     void WriteReg(u32 method, u32 value);
+
+    /**
+     * Handles a method call to this engine.
+     * @param method Method to call
+     * @param parameters Arguments to the method call
+     */
+    void CallMethod(u32 method, const std::vector<u32>& parameters);
 };
 
 } // namespace Engines