diff options
| author | Rodrigo Locatti <reinuseslisp@airmail.cc> | 2019-09-21 23:06:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-21 23:06:07 +0200 |
| commit | 9286976948f10d73e63a8b682c28f012221a2b03 (patch) | |
| tree | c32104c38b496848992ee0d1991ba555cd63fac0 /src/video_core/shader/decode | |
| parent | Merge pull request #2885 from Hexagon12/port-4944 (diff) | |
| parent | Shader_IR: ICMP corrections and fixes (diff) | |
| download | yuzu-9286976948f10d73e63a8b682c28f012221a2b03.tar yuzu-9286976948f10d73e63a8b682c28f012221a2b03.tar.gz yuzu-9286976948f10d73e63a8b682c28f012221a2b03.tar.bz2 yuzu-9286976948f10d73e63a8b682c28f012221a2b03.tar.lz yuzu-9286976948f10d73e63a8b682c28f012221a2b03.tar.xz yuzu-9286976948f10d73e63a8b682c28f012221a2b03.tar.zst yuzu-9286976948f10d73e63a8b682c28f012221a2b03.zip | |
Diffstat (limited to 'src/video_core/shader/decode')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index c8c1a7f40..b73f6536e 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -138,6 +138,35 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { SetRegister(bb, instr.gpr0, value); break; } + case OpCode::Id::ICMP_CR: + case OpCode::Id::ICMP_R: + case OpCode::Id::ICMP_RC: + case OpCode::Id::ICMP_IMM: { + const Node zero = Immediate(0); + + const auto [op_b, test] = [&]() -> std::pair<Node, Node> { + switch (opcode->get().GetId()) { + case OpCode::Id::ICMP_CR: + return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset), + GetRegister(instr.gpr39)}; + case OpCode::Id::ICMP_R: + return {GetRegister(instr.gpr20), GetRegister(instr.gpr39)}; + case OpCode::Id::ICMP_RC: + return {GetRegister(instr.gpr39), + GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)}; + case OpCode::Id::ICMP_IMM: + return {Immediate(instr.alu.GetSignedImm20_20()), GetRegister(instr.gpr39)}; + default: + UNREACHABLE(); + return {zero, zero}; + } + }(); + const Node op_a = GetRegister(instr.gpr8); + const Node comparison = + GetPredicateComparisonInteger(instr.icmp.cond, instr.icmp.is_signed != 0, test, zero); + SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_a, op_b)); + break; + } case OpCode::Id::LOP_C: case OpCode::Id::LOP_R: case OpCode::Id::LOP_IMM: { |