8 files changed, 59 insertions, 12 deletions

diff --git a/src/shader_recompiler/CMakeLists.txt b/src/shader_recompiler/CMakeLists.txt
index 14dc51b5f..b4d2dcc42 100644
--- a/src/shader_recompiler/CMakeLists.txt
+++ b/src/shader_recompiler/CMakeLists.txt
@@ -69,6 +69,7 @@ add_library(shader_recompiler STATIC
     frontend/maxwell/translate/impl/impl.cpp
     frontend/maxwell/translate/impl/impl.h
     frontend/maxwell/translate/impl/integer_add.cpp
+    frontend/maxwell/translate/impl/integer_popcount.cpp
     frontend/maxwell/translate/impl/integer_scaled_add.cpp
     frontend/maxwell/translate/impl/integer_set_predicate.cpp
     frontend/maxwell/translate/impl/integer_shift_left.cpp
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 90afbcc90..64c8e9ef6 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -228,6 +228,8 @@ Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count)
 Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
 Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
 Id EmitBitReverse32(EmitContext& ctx, Id value);
+Id EmitBitCount32(EmitContext& ctx, Id value);
+Id EmitBitwiseNot32(EmitContext& ctx, Id a);
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 406df1b78..e49ca7bde 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -106,6 +106,14 @@ Id EmitBitReverse32(EmitContext& ctx, Id value) {
     return ctx.OpBitReverse(ctx.U32[1], value);
 }
 
+Id EmitBitCount32(EmitContext& ctx, Id value) {
+    return ctx.OpBitCount(ctx.U32[1], value);
+}
+
+Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
+    return ctx.OpNot(ctx.U32[1], a);
+}
+
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
     return ctx.OpSLessThan(ctx.U1, lhs, rhs);
 }
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 7c3908398..54fdf9559 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -808,6 +808,14 @@ U32 IREmitter::BitReverse(const U32& value) {
     return Inst<U32>(Opcode::BitReverse32, value);
 }
 
+U32 IREmitter::BitCount(const U32& value) {
+    return Inst<U32>(Opcode::BitCount32, value);
+}
+
+U32 IREmitter::BitwiseNot(const U32& a) {
+    return Inst<U32>(Opcode::BitwiseNot32, a);
+}
+
 U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
     return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
 }
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index f7998e156..9dec22145 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -160,6 +160,8 @@ public:
     [[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count,
                                       bool is_signed);
     [[nodiscard]] U32 BitReverse(const U32& value);
+    [[nodiscard]] U32 BitCount(const U32& value);
+    [[nodiscard]] U32 BitwiseNot(const U32& a);
 
     [[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
     [[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs);
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index f420f1161..59a13e911 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -232,6 +232,8 @@ OPCODE(BitFieldInsert,                                      U32,            U32,
 OPCODE(BitFieldSExtract,                                    U32,            U32,            U32,            U32,                            )
 OPCODE(BitFieldUExtract,                                    U32,            U32,            U32,            U32,                            )
 OPCODE(BitReverse32,                                        U32,            U32,                                                            )
+OPCODE(BitCount32,                                          U32,            U32,                                                            )
+OPCODE(BitwiseNot32,                                        U32,            U32,                                                            )
 
 OPCODE(SLessThan,                                           U1,             U32,            U32,                                            )
 OPCODE(ULessThan,                                           U1,             U32,            U32,                                            )
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_popcount.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_popcount.cpp
new file mode 100644
index 000000000..5ece7678d
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_popcount.cpp
@@ -0,0 +1,36 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/bit_field.h"
+#include "common/common_types.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+namespace {
+void POPC(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
+    union {
+        u64 raw;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<40, 1, u64> tilde;
+    } const popc{insn};
+
+    const IR::U32 operand = popc.tilde == 0 ? src : v.ir.BitwiseNot(src);
+    const IR::U32 result = v.ir.BitCount(operand);
+    v.X(popc.dest_reg, result);
+}
+} // Anonymous namespace
+
+void TranslatorVisitor::POPC_reg(u64 insn) {
+    POPC(*this, insn, GetReg20(insn));
+}
+
+void TranslatorVisitor::POPC_cbuf(u64 insn) {
+    POPC(*this, insn, GetCbuf(insn));
+}
+
+void TranslatorVisitor::POPC_imm(u64 insn) {
+    POPC(*this, insn, GetImm20(insn));
+}
+
+} // namespace Shader::Maxwell
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index 45ed04e25..127686b43 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -653,18 +653,6 @@ void TranslatorVisitor::PLONGJMP(u64) {
     ThrowNotImplemented(Opcode::PLONGJMP);
 }
 
-void TranslatorVisitor::POPC_reg(u64) {
-    ThrowNotImplemented(Opcode::POPC_reg);
-}
-
-void TranslatorVisitor::POPC_cbuf(u64) {
-    ThrowNotImplemented(Opcode::POPC_cbuf);
-}
-
-void TranslatorVisitor::POPC_imm(u64) {
-    ThrowNotImplemented(Opcode::POPC_imm);
-}
-
 void TranslatorVisitor::PRET(u64) {
     ThrowNotImplemented(Opcode::PRET);
 }