diff options
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 11 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 9 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 939a71022..f495b623b 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -290,6 +290,11 @@ union Instruction { union { BitField<39, 3, u64> pred; + BitField<42, 1, u64> neg_pred; + } sel; + + union { + BitField<39, 3, u64> pred; BitField<42, 1, u64> negate_pred; BitField<43, 2, IMinMaxExchange> exchange; BitField<48, 1, u64> is_signed; @@ -513,6 +518,9 @@ public: ISCADD_C, // Scale and Add ISCADD_R, ISCADD_IMM, + SEL_C, + SEL_R, + SEL_IMM, MUFU, // Multi-Function Operator RRO_C, // Range Reduction Operator RRO_R, @@ -713,6 +721,9 @@ private: INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), + INST("0100110010100---", Id::SEL_C, Type::ArithmeticInteger, "SEL_C"), + INST("0101110010100---", Id::SEL_R, Type::ArithmeticInteger, "SEL_R"), + INST("0011100010100---", Id::SEL_IMM, Type::ArithmeticInteger, "SEL_IMM"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index b48d30466..bfbfc3ac2 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -1139,6 +1139,15 @@ private: "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1); break; } + case OpCode::Id::SEL_C: + case OpCode::Id::SEL_R: + case OpCode::Id::SEL_IMM: { + std::string condition = + GetPredicateCondition(instr.sel.pred, instr.sel.neg_pred != 0); + regs.SetRegisterToInteger(instr.gpr0, true, 0, + '(' + condition + ") ? " + op_a + " : " + op_b, 1, 1); + break; + } case OpCode::Id::LOP_C: case OpCode::Id::LOP_R: case OpCode::Id::LOP_IMM: { |