1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
|
// Copyright 2014 Citra Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <cstring>
#include "common/make_unique.h"
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
#include "core/arm/dyncom/arm_dyncom.h"
#include "core/arm/dyncom/arm_dyncom_interpreter.h"
#include "core/arm/dyncom/arm_dyncom_run.h"
#include "core/core.h"
#include "core/core_timing.h"
ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
state = Common::make_unique<ARMul_State>();
ARMul_NewState(state.get());
ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->abort_model = ABORT_BASE_RESTORED;
state->bigendSig = LOW;
state->lateabtSig = LOW;
state->NirqSig = HIGH;
// Reset the core to initial state
ARMul_Reset(state.get());
state->Emulate = RUN;
// Switch to the desired privilege mode.
switch_mode(state.get(), initial_mode);
state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
state->Reg[15] = 0x00000000;
}
ARM_DynCom::~ARM_DynCom() {
}
void ARM_DynCom::SetPC(u32 pc) {
state->Reg[15] = pc;
}
u32 ARM_DynCom::GetPC() const {
return state->Reg[15];
}
u32 ARM_DynCom::GetReg(int index) const {
return state->Reg[index];
}
void ARM_DynCom::SetReg(int index, u32 value) {
state->Reg[index] = value;
}
u32 ARM_DynCom::GetCPSR() const {
return state->Cpsr;
}
void ARM_DynCom::SetCPSR(u32 cpsr) {
state->Cpsr = cpsr;
}
u32 ARM_DynCom::GetCP15Register(CP15Register reg) {
return state->CP15[reg];
}
void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
state->CP15[reg] = value;
}
void ARM_DynCom::AddTicks(u64 ticks) {
down_count -= ticks;
if (down_count < 0)
CoreTiming::Advance();
}
void ARM_DynCom::ExecuteInstructions(int num_instructions) {
state->NumInstrsToExecute = num_instructions;
// Dyncom only breaks on instruction dispatch. This only happens on every instruction when
// executing one instruction at a time. Otherwise, if a block is being executed, more
// instructions may actually be executed than specified.
unsigned ticks_executed = InterpreterMainLoop(state.get());
AddTicks(ticks_executed);
}
void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) {
memset(&context, 0, sizeof(Core::ThreadContext));
context.cpu_registers[0] = arg;
context.pc = entry_point;
context.sp = stack_top;
context.cpsr = 0x1F; // Usermode
}
void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
ctx.sp = state->Reg[13];
ctx.lr = state->Reg[14];
ctx.pc = state->Reg[15];
ctx.cpsr = state->Cpsr;
ctx.fpscr = state->VFP[1];
ctx.fpexc = state->VFP[2];
}
void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
state->Reg[13] = ctx.sp;
state->Reg[14] = ctx.lr;
state->Reg[15] = ctx.pc;
state->Cpsr = ctx.cpsr;
state->VFP[1] = ctx.fpscr;
state->VFP[2] = ctx.fpexc;
}
void ARM_DynCom::PrepareReschedule() {
state->NumInstrsToExecute = 0;
}
|
