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-rw-r--r--private/mvdm/softpc.new/host/inc/mips/prod/gldc_c.h185
1 files changed, 185 insertions, 0 deletions
diff --git a/private/mvdm/softpc.new/host/inc/mips/prod/gldc_c.h b/private/mvdm/softpc.new/host/inc/mips/prod/gldc_c.h
new file mode 100644
index 000000000..50e2fc476
--- /dev/null
+++ b/private/mvdm/softpc.new/host/inc/mips/prod/gldc_c.h
@@ -0,0 +1,185 @@
+#ifndef _Gldc_c_h
+#define _Gldc_c_h
+#define N_RPL_BITS (2)
+#define RPL_MASK (3)
+#define NOT_RPL_MASK (65532)
+#define N_GL_SELECTORS (16384)
+#define N_IDT_SELECTORS (256)
+#define N_CPLS (4)
+#define N_RPLS (4)
+#define TI_P (2)
+#define SEL_S (15)
+#define SEL_E (2)
+#define INTEL_SEL_S (31)
+#define INTEL_SEL_E (16)
+#define INTEL_P (15)
+#define INTEL_X (22)
+#define INTEL_G (23)
+#define INTEL_AR_ZERO (21)
+#define INTEL_AVL (20)
+#define INTEL_HI_LIMIT_S (19)
+#define INTEL_HI_LIMIT_E (16)
+#define INTEL_HI_LIMIT_SHIFT (16)
+#define INTEL_LO_LIMIT_S (15)
+#define INTEL_LO_LIMIT_E (0)
+#define INTEL_DPL_S (14)
+#define INTEL_DPL_E (13)
+#define INTEL_SUPERTYPE_S (12)
+#define INTEL_SUPERTYPE_E (8)
+#define INTEL_HI_BASE_S (31)
+#define INTEL_HI_BASE_E (24)
+#define INTEL_MID_BASE_S (7)
+#define INTEL_MID_BASE_E (0)
+#define INTEL_LO_BASE_S (31)
+#define INTEL_LO_BASE_E (16)
+#define INTEL_HI_BASE_SHIFT (24)
+#define INTEL_MID_BASE_SHIFT (16)
+#define INTEL_SELECTOR_S (31)
+#define INTEL_SELECTOR_E (16)
+#define INTEL_HI_OFFSET_S (31)
+#define INTEL_HI_OFFSET_E (16)
+#define INTEL_TOP_AR_S (23)
+#define INTEL_TOP_AR_E (16)
+#define INTEL_BOTTOM_AR_S (15)
+#define INTEL_BOTTOM_AR_E (8)
+#define AR_G (15)
+#define AR2_X_BIT (6)
+#define AR2_G_BIT (7)
+#define AR_SUPERTYPE_S (4)
+#define AR_SUPERTYPE_E (0)
+#define EAR_SUPERTYPE_MASK (31)
+#define EAR_SUPERTYPE_S (4)
+#define EAR_SUPERTYPE_E (0)
+#define EAR_A_MASK (1)
+#define EAR_A (0)
+#define EAR_DPL_MASK (96)
+#define EAR_DPL_S (6)
+#define EAR_DPL_E (5)
+#define EAR_P_MASK (128)
+#define EAR_P (7)
+#define EAR_AR_MASK (255)
+#define EAR_AR_S (7)
+#define EAR_AR_E (0)
+#define EAR_NR_BITS_MASK (3840)
+#define EAR_NR_BITS_S (11)
+#define EAR_NR_BITS_E (8)
+#define EAR_CD_MASK (4096)
+#define EAR_CD (12)
+#define EAR_NG_BITS_MASK (57344)
+#define EAR_NG_BITS_S (15)
+#define EAR_NG_BITS_E (13)
+#define EAR_NX_BITS_MASK (983040)
+#define EAR_NX_BITS_S (19)
+#define EAR_NX_BITS_E (16)
+#define EAR_NC_MASK (1048576)
+#define EAR_NC (20)
+#define EAR_NW_MASK (2097152)
+#define EAR_NW (21)
+#define EAR_NA_MASK (4194304)
+#define EAR_NA (22)
+#define EAR_NP_MASK (8388608)
+#define EAR_NP (23)
+#define EAR_NCD_MASK (16777216)
+#define EAR_NCD (24)
+#define EAR_CONTEXT_MASK (2113929216)
+#define EAR_CONTEXT_S (30)
+#define EAR_CONTEXT_E (25)
+#define EAR_CDODGY_MASK (-2147483648)
+#define EAR_CDODGY (31)
+#define GPH_LDTH_MASK (1032192)
+#define GPH_LDTH_BITS_S (19)
+#define GPH_LDTH_BITS_E (14)
+#define GPH_SEL_MASK (16383)
+#define GPH_SEL_BITS_S (13)
+#define GPH_SEL_BITS_E (0)
+#define ST_AVAILABLE_TSS (1)
+#define ST_LDT_SEGMENT (2)
+#define ST_BUSY_TSS (3)
+#define ST_CALL_GATE (4)
+#define ST_TASK_GATE (5)
+#define ST_INTERRUPT_GATE (6)
+#define ST_TRAP_GATE (7)
+#define ST_INVALID (8)
+#define ST_XTND_AVAILABLE_TSS (9)
+#define ST_GLDC_DUMMY (10)
+#define ST_XTND_BUSY_TSS (11)
+#define ST_XTND_CALL_GATE (12)
+#define ST_GLDC_NULL (13)
+#define ST_XTND_INTERRUPT_GATE (14)
+#define ST_XTND_TRAP_GATE (15)
+#define ST_EXPANDUP_READONLY_DATA (17)
+#define ST_EXPANDUP_WRITEABLE_DATA (19)
+#define ST_EXPANDDOWN_READONLY_DATA (21)
+#define ST_EXPANDDOWN_WRITEABLE_DATA (23)
+#define ST_NONCONFORM_NOREAD_CODE (25)
+#define ST_NONCONFORM_READABLE_CODE (27)
+#define ST_CONFORM_NOREAD_CODE (29)
+#define ST_CONFORM_READABLE_CODE (31)
+#define NUM_LDTS (7)
+#define LDT_NOT_IN_USE (65535)
+#define GLDC_INDEX_TABLE_SIZE (16384)
+#define DESC_IS_LOCAL (4)
+#define SEGMENT_IS_WRITEABLE (8)
+#define DESC_IS_DELETED (16)
+#define GLDC_RECNULL ((struct GLDC_REC*)0)
+#define IDC_RECNULL ((struct IDC_REC*)0)
+#define CR_GUARANTEED_BAD (-2147483617)
+#define GLDC_LdDs (0)
+#define GLDC_LdSs (4)
+#define GLDC_LdCsForCJ (8)
+#define GLDC_LdCsForRet (12)
+#define GLDC_LdCsForRetRing (16)
+#define GLDC_GtCJ (20)
+#define GLDC_GtDestCall (21)
+#define GLDC_CrCPLSize (22)
+#define GLDC_CrLDTSize (88)
+#define IDC_NIS_MASK (-16)
+#define IDC_NIS_S (31)
+#define IDC_NIS_E (4)
+#define IDC_NP (3)
+#define IDC_NP_MASK (8)
+#define IDC_CPL_MASK (3)
+#define IDC_CPL_S (2)
+#define IDC_CPL_E (0)
+#define IDC_IDT_NUM_S (12)
+#define IDC_IDT_NUM_E (8)
+#define IDC_INT_NUM_S (7)
+#define IDC_INT_NUM_E (0)
+#define IDC_LOWEST_SEQ_VAL (0)
+#define IDC_INITIAL_CONTROL_VAL (-8)
+#define IDC_ILLEGAL_EIAR (-1)
+#define NO_PARAMS (0)
+struct GLDC_REC
+{
+ IU32 ear;
+ IU32 base;
+ IU32 cookie;
+ IU32 lowerRdWrBound;
+ IU32 upperRdWrBound;
+ IU8 arTopByte;
+ IU8 flags;
+ IU16 next;
+ IU32 glimit;
+ IU32 intelAddress;
+};
+struct IDC_REC
+{
+ IU32 eiar;
+ IU16 sel;
+ IU8 type;
+ IU8 context;
+ IU32 offset;
+ IU32 intelAddress;
+};
+struct SEG_STRUCT
+{
+ IU32 rlimit2;
+ IU32 wlimit2;
+};
+struct IDC_BASE_LIMIT_CONTEXT
+{
+ IU32 base;
+ IU16 limit;
+ IU8 context;
+};
+#endif /* ! _Gldc_c_h */