summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 03:54:47 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commit7c192ec43fb6a08baea5d55aa47fcf3fa98d4343 (patch)
tree5d2db428128c0972877566bc6fc685e2a3a43525
parentshader_decode: Implement MOV_C and MOV_R (diff)
downloadyuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.tar
yuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.tar.gz
yuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.tar.bz2
yuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.tar.lz
yuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.tar.xz
yuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.tar.zst
yuzu-7c192ec43fb6a08baea5d55aa47fcf3fa98d4343.zip
-rw-r--r--src/video_core/shader/decode/arithmetic.cpp42
1 files changed, 42 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp
index c297f729e..78bca79e3 100644
--- a/src/video_core/shader/decode/arithmetic.cpp
+++ b/src/video_core/shader/decode/arithmetic.cpp
@@ -36,6 +36,48 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
SetRegister(bb, instr.gpr0, op_b);
break;
}
+ case OpCode::Id::FMUL_C:
+ case OpCode::Id::FMUL_R:
+ case OpCode::Id::FMUL_IMM: {
+ // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
+ UNIMPLEMENTED_IF_MSG(instr.fmul.tab5cb8_2 != 0, "FMUL tab5cb8_2({}) is not implemented",
+ instr.fmul.tab5cb8_2.Value());
+ UNIMPLEMENTED_IF_MSG(
+ instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented",
+ instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default
+ UNIMPLEMENTED_IF_MSG(instr.generates_cc,
+ "Condition codes generation in FMUL is not implemented");
+
+ op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);
+
+ // TODO(Rodrigo): Should precise be used when there's a postfactor?
+ Node value = Operation(OperationCode::FMul, PRECISE, op_a, op_b);
+
+ if (instr.fmul.postfactor != 0) {
+ auto postfactor = static_cast<s32>(instr.fmul.postfactor);
+
+ // Postfactor encoded as 3-bit 1's complement in instruction, interpreted with below
+ // logic.
+ if (postfactor >= 4) {
+ postfactor = 7 - postfactor;
+ } else {
+ postfactor = 0 - postfactor;
+ }
+
+ if (postfactor > 0) {
+ value = Operation(OperationCode::FMul, NO_PRECISE, value,
+ Immediate(static_cast<f32>(1 << postfactor)));
+ } else {
+ value = Operation(OperationCode::FDiv, NO_PRECISE, value,
+ Immediate(static_cast<f32>(1 << -postfactor)));
+ }
+ }
+
+ value = GetSaturatedFloat(value, instr.alu.saturate_d);
+
+ SetRegister(bb, instr.gpr0, value);
+ break;
+ }
default:
UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
}