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author | wwylele <wwylele@gmail.com> | 2016-06-27 20:38:49 +0200 |
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committer | wwylele <wwylele@gmail.com> | 2016-08-27 15:38:06 +0200 |
commit | 2161f52661f9866161165db480594672307940ad (patch) | |
tree | 5a8bb26803b0b521e9d1dcb8570210d8d5b393a8 /src/core/arm/dyncom/arm_dyncom.cpp | |
parent | Memory: add ReadCString function (diff) | |
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Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom.cpp')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index 13492a08b..ab77da965 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp @@ -12,6 +12,7 @@ #include "core/arm/dyncom/arm_dyncom.h" #include "core/arm/dyncom/arm_dyncom_interpreter.h" #include "core/arm/dyncom/arm_dyncom_run.h" +#include "core/arm/dyncom/arm_dyncom_trans.h" #include "core/core.h" #include "core/core_timing.h" @@ -23,6 +24,11 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) { ARM_DynCom::~ARM_DynCom() { } +void ARM_DynCom::ClearInstructionCache() { + state->instruction_cache.clear(); + trans_cache_buf_top = 0; +} + void ARM_DynCom::SetPC(u32 pc) { state->Reg[15] = pc; } |