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authorMai M <mathew1800@gmail.com>2022-04-24 23:43:31 +0200
committerGitHub <noreply@github.com>2022-04-24 23:43:31 +0200
commit9d642539167f8429359670f6d4476d46ff8982ad (patch)
tree2baae9e2c1a57c8d26be9ed8d117958f69f3882f /src/core/arm
parentMerge pull request #8249 from german77/queued (diff)
parentRemove unused PrepareReschedule function (diff)
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Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h3
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.cpp4
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.h1
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp4
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.h1
5 files changed, 0 insertions, 13 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index bcec4b3b8..8ce973a77 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -174,9 +174,6 @@ public:
/// Clears the exclusive monitor's state.
virtual void ClearExclusiveState() = 0;
- /// Prepare core for thread reschedule (if needed to correctly handle state)
- virtual void PrepareReschedule() = 0;
-
/// Signal an interrupt and ask the core to halt as soon as possible.
virtual void SignalInterrupt() = 0;
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 60e9edff2..781a77f6f 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -327,10 +327,6 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
jit.load()->LoadContext(context);
}
-void ARM_Dynarmic_32::PrepareReschedule() {
- jit.load()->HaltExecution(break_loop);
-}
-
void ARM_Dynarmic_32::SignalInterrupt() {
jit.load()->HaltExecution(break_loop);
}
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h
index a25c9d277..abfe76644 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.h
@@ -57,7 +57,6 @@ public:
void LoadContext(const ThreadContext32& ctx) override;
void LoadContext(const ThreadContext64& ctx) override {}
- void PrepareReschedule() override;
void SignalInterrupt() override;
void ClearExclusiveState() override;
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index d8d3a38db..1b1334598 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -395,10 +395,6 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
SetTPIDR_EL0(ctx.tpidr);
}
-void ARM_Dynarmic_64::PrepareReschedule() {
- jit.load()->HaltExecution(break_loop);
-}
-
void ARM_Dynarmic_64::SignalInterrupt() {
jit.load()->HaltExecution(break_loop);
}
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h
index 9680c7b99..01a7e4dad 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.h
@@ -51,7 +51,6 @@ public:
void LoadContext(const ThreadContext32& ctx) override {}
void LoadContext(const ThreadContext64& ctx) override;
- void PrepareReschedule() override;
void SignalInterrupt() override;
void ClearExclusiveState() override;