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authorameerj <52414509+ameerj@users.noreply.github.com>2021-03-24 01:27:17 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:24 +0200
commit3d07cef009cf9e287744c7771c67166ef5761ce8 (patch)
tree78f4fea18d9facb72850b4c2fe115e96b7af8f26 /src/shader_recompiler/backend/spirv/emit_spirv.h
parentvk_pipeline_cache: Fix ReleaseContents order (diff)
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Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv.h')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 960d022ff..ce23200f2 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -346,5 +346,9 @@ Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Va
Id coords, Id dref, Id bias_lc, Id offset);
Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
Id coords, Id dref, Id lod_lc, Id offset);
+Id EmitVoteAll(EmitContext& ctx, Id pred);
+Id EmitVoteAny(EmitContext& ctx, Id pred);
+Id EmitVoteEqual(EmitContext& ctx, Id pred);
+Id EmitSubgroupBallot(EmitContext& ctx, Id pred);
} // namespace Shader::Backend::SPIRV