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| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-04-12 00:16:12 +0200 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-23 03:51:27 +0200 |
| commit | 5c61e860e4f83524ffce10ca447398e83de81640 (patch) | |
| tree | ff19c70e70170715c1de763d9674bf35d4aa5c42 /src/shader_recompiler/frontend/maxwell/translate/impl | |
| parent | shader: Apply sign bit in FCMP (imm) (diff) | |
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Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp index be1f21e7b..50650cc56 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp @@ -113,6 +113,8 @@ enum class SpecialRegister : u64 { [[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) { switch (special_register) { + case SpecialRegister::SR_THREAD_KILL: + return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))}; case SpecialRegister::SR_TID_X: return ir.LocalInvocationIdX(); case SpecialRegister::SR_TID_Y: |